.prio_mask = 7,
},
[17] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
.force = IPIC_SEFCR,
.prio_mask = 5,
},
[18] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
.force = IPIC_SEFCR,
.prio_mask = 6,
},
[19] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
.force = IPIC_SEFCR,
.prio_mask = 7,
},
[20] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
.force = IPIC_SEFCR,
.prio_mask = 4,
},
[21] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
.force = IPIC_SEFCR,
.prio_mask = 5,
},
[22] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
.force = IPIC_SEFCR,
.prio_mask = 6,
},
[23] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
.force = IPIC_SEFCR,
ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
for (i = 0 ; i < NR_IPIC_INTS ; i++) {
- irq_desc[i+irq_offset].handler = &ipic;
+ irq_desc[i+irq_offset].chip = &ipic;
irq_desc[i+irq_offset].status = IRQ_LEVEL;
}