fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / arch / ppc / syslib / ppc8xx_pic.c

diff --git a/arch/ppc/syslib/ppc8xx_pic.c b/arch/ppc/syslib/ppc8xx_pic.c
index d3b01c6..e8619c7 100644 (file)
--- a/arch/ppc/syslib/ppc8xx_pic.c
+++ b/arch/ppc/syslib/ppc8xx_pic.c
@@ -1,4 +1,3 @@
-#include <linux/config.h>
 #include <linux/module.h>
 #include <linux/stddef.h>
 #include <linux/init.h>
@@ -6,11 +5,12 @@
 #include <linux/signal.h>
 #include <linux/interrupt.h>
 #include <asm/irq.h>
+#include <asm/io.h>
 #include <asm/8xx_immap.h>
 #include <asm/mpc8xx.h>
 #include "ppc8xx_pic.h"
 
-extern int cpm_get_irq(struct pt_regs *regs);
+extern int cpm_get_irq(void);
 
 /* The 8xx internal interrupt controller.  It is usually
  * the only interrupt controller.  Some boards, like the MBX and
@@ -29,8 +29,7 @@ static void m8xx_mask_irq(unsigned int irq_nr)
        word = irq_nr >> 5;
 
        ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
-       ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
-                                               ppc_cached_irq_mask[word];
+       out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
 }
 
 static void m8xx_unmask_irq(unsigned int irq_nr)
@@ -41,8 +40,7 @@ static void m8xx_unmask_irq(unsigned int irq_nr)
        word = irq_nr >> 5;
 
        ppc_cached_irq_mask[word] |= (1 << (31-bit));
-       ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
-                                               ppc_cached_irq_mask[word];
+       out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
 }
 
 static void m8xx_end_irq(unsigned int irq_nr)
@@ -55,8 +53,7 @@ static void m8xx_end_irq(unsigned int irq_nr)
                word = irq_nr >> 5;
 
                ppc_cached_irq_mask[word] |= (1 << (31-bit));
-               ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
-                       ppc_cached_irq_mask[word];
+               out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
        }
 }
 
@@ -69,9 +66,8 @@ static void m8xx_mask_and_ack(unsigned int irq_nr)
        word = irq_nr >> 5;
 
        ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
-       ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask =
-                                               ppc_cached_irq_mask[word];
-       ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = 1 << (31-bit);
+       out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
+       out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend, 1 << (31-bit));
 }
 
 struct hw_interrupt_type ppc8xx_pic = {
@@ -93,14 +89,14 @@ m8xx_get_irq(struct pt_regs *regs)
        /* For MPC8xx, read the SIVEC register and shift the bits down
         * to get the irq number.
         */
-       irq = ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26;
+       irq = in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec) >> 26;
 
        /*
         * When we read the sivec without an interrupt to process, we will
         * get back SIU_LEVEL7.  In this case, return -1
         */
         if (irq == CPM_INTERRUPT)
-               irq = CPM_IRQ_OFFSET + cpm_get_irq(regs);
+               irq = CPM_IRQ_OFFSET + cpm_get_irq();
 #if defined(CONFIG_PCI)
        else if (irq == ISA_BRIDGE_INT) {
                int isa_irq;