#include <asm/offsets.h>
#include <asm/bug.h>
#include <asm/cputable.h>
-#include <asm/setup.h>
#ifdef CONFIG_PPC_ISERIES
#define DO_SOFT_DISABLE
/*
* hcall interface to pSeries LPAR
*/
-#define HVSC .long 0x44000022
-#define H_SET_ASR 0x30
+#define HVSC .long 0x44000022
+#define H_SET_ASR 0x30
/*
* We layout physical memory as follows:
* 0x3000 - 0x3fff : Interrupt support
* 0x4000 - 0x4fff : NACA
* 0x5000 - 0x5fff : SystemCfg
- * 0x6000 : iSeries and common interrupt prologs
+ * 0x6000 : iSeries and common interrupt prologs
* 0x9000 - 0x9fff : Initial segment table
*/
/*
* SPRG Usage
*
- * Register Definition
+ * Register Definition
*
- * SPRG0 reserved for hypervisor
- * SPRG1 temp - used to save gpr
- * SPRG2 temp - used to save gpr
- * SPRG3 virt addr of paca
+ * SPRG0 reserved for hypervisor
+ * SPRG1 temp - used to save gpr
+ * SPRG2 temp - used to save gpr
+ * SPRG3 virt addr of paca
*/
/*
* to the pidhash table (also used by the debugger)
*/
.llong msChunks-KERNELBASE
- .llong 0 /* pidhash-KERNELBASE SFRXXX */
+ .llong 0 /* pidhash-KERNELBASE SFRXXX */
/* Offset 0x38 - Pointer to start of embedded System.map */
.globl embedded_sysmap_start
/* Secondary processors spin on this value until it goes to 1. */
.globl __secondary_hold_spinloop
__secondary_hold_spinloop:
- .llong 0x0
+ .llong 0x0
/* Secondary processors write this value with their cpu # */
- /* after they enter the spin loop immediately below. */
- .globl __secondary_hold_acknowledge
+ /* after they enter the spin loop immediately below. */
+ .globl __secondary_hold_acknowledge
__secondary_hold_acknowledge:
- .llong 0x0
+ .llong 0x0
. = 0x60
/*
mtmsrd r24 /* RI on */
/* Grab our linux cpu number */
- mr r24,r3
+ mr r24,r3
/* Tell the master cpu we're here */
/* Relocation is off & we are located at an address less */
/* than 0x100, so only need to grab low order offset. */
- std r24,__secondary_hold_acknowledge@l(0)
+ std r24,__secondary_hold_acknowledge@l(0)
sync
/* All secondary cpu's wait here until told to start. */
-100: ld r4,__secondary_hold_spinloop@l(0)
- cmpdi 0,r4,1
- bne 100b
+100: ld r4,__secondary_hold_spinloop@l(0)
+ cmpdi 0,r4,1
+ bne 100b
#ifdef CONFIG_HMT
b .hmt_init
#else
#ifdef CONFIG_SMP
- mr r3,r24
- b .pseries_secondary_smp_init
+ mr r3,r24
+ b .pseries_secondary_smp_init
#else
BUG_OPCODE
#endif
#define EX_R13 32
#define EX_SRR0 40
#define EX_DAR 48
-#define EX_LR 48 /* SLB miss saves LR, but not DAR */
#define EX_DSISR 56
-#define EX_CCR 60
+#define EX_CCR 60
#define EXCEPTION_PROLOG_PSERIES(area, label) \
mfspr r13,SPRG3; /* get paca address into r13 */ \
mtspr SRR0,r12; \
mfspr r12,SRR1; /* and SRR1 */ \
mtspr SRR1,r10; \
- rfid; \
- b . /* prevent speculative execution */
+ rfid
/*
* This is the start of the interrupt handlers for iSeries
#define EXCEPTION_PROLOG_ISERIES_2 \
mfmsr r10; \
- ld r11,PACALPPACA+LPPACASRR0(r13); \
- ld r12,PACALPPACA+LPPACASRR1(r13); \
+ ld r11,LPPACA+LPPACASRR0(r13); \
+ ld r12,LPPACA+LPPACASRR1(r13); \
ori r10,r10,MSR_RI; \
mtmsrd r10,1
#define EXCEPTION_PROLOG_COMMON(n, area) \
andi. r10,r12,MSR_PR; /* See if coming from user */ \
mr r10,r1; /* Save r1 */ \
- subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
- beq- 1f; \
+ subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
+ beq- 1f; \
ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
-1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
+1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
bge- cr1,bad_stack; /* abort if it is */ \
std r9,_CCR(r1); /* save CR in stackframe */ \
std r11,_NIP(r1); /* save SRR0 in stackframe */ \
/*
* Exception vectors.
*/
-#define STD_EXCEPTION_PSERIES(n, label) \
+#define STD_EXCEPTION_PSERIES(n, label ) \
. = n; \
.globl label##_Pseries; \
label##_Pseries: \
- HMT_MEDIUM; \
mtspr SPRG1,r13; /* save r13 */ \
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
#define STD_EXCEPTION_ISERIES(n, label, area) \
.globl label##_Iseries; \
label##_Iseries: \
- HMT_MEDIUM; \
mtspr SPRG1,r13; /* save r13 */ \
EXCEPTION_PROLOG_ISERIES_1(area); \
EXCEPTION_PROLOG_ISERIES_2; \
b label##_common
-#define MASKABLE_EXCEPTION_ISERIES(n, label) \
+#define MASKABLE_EXCEPTION_ISERIES( n, label ) \
.globl label##_Iseries; \
label##_Iseries: \
- HMT_MEDIUM; \
mtspr SPRG1,r13; /* save r13 */ \
EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
lbz r10,PACAPROFENABLED(r13); \
EXCEPTION_PROLOG_ISERIES_2; \
b label##_common; \
label##_Iseries_profile: \
- ld r12,PACALPPACA+LPPACASRR1(r13); \
+ ld r12,LPPACA+LPPACASRR1(r13); \
andi. r12,r12,MSR_PR; /* Test if in kernel */ \
bne label##_Iseries_prof_ret; \
- ld r11,PACALPPACA+LPPACASRR0(r13); \
+ ld r11,LPPACA+LPPACASRR0(r13); \
ld r12,PACAPROFSTEXT(r13); /* _stext */ \
subf r11,r12,r11; /* offset into kernel */ \
lwz r12,PACAPROFSHIFT(r13); \
#endif
-#define STD_EXCEPTION_COMMON(trap, label, hdlr) \
+#define STD_EXCEPTION_COMMON( trap, label, hdlr ) \
.align 7; \
.globl label##_common; \
label##_common: \
DISABLE_INTS; \
bl .save_nvgprs; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
- bl hdlr; \
- b .ret_from_except
+ bl hdlr; \
+ b .ret_from_except
#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
.align 7; \
.globl __start_interrupts
__start_interrupts:
- STD_EXCEPTION_PSERIES(0x100, SystemReset)
+ STD_EXCEPTION_PSERIES( 0x100, SystemReset )
. = 0x200
+ .globl MachineCheck_Pseries
_MachineCheckPseries:
- HMT_MEDIUM
mtspr SPRG1,r13 /* save r13 */
EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
. = 0x300
.globl DataAccess_Pseries
DataAccess_Pseries:
- HMT_MEDIUM
mtspr SPRG1,r13
BEGIN_FTR_SECTION
mtspr SPRG2,r12
. = 0x380
.globl DataAccessSLB_Pseries
DataAccessSLB_Pseries:
- HMT_MEDIUM
- mtspr SPRG1,r13
- mfspr r13,SPRG3 /* get paca address into r13 */
- std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
- std r10,PACA_EXSLB+EX_R10(r13)
- std r11,PACA_EXSLB+EX_R11(r13)
- std r12,PACA_EXSLB+EX_R12(r13)
- std r3,PACASLBR3(r13)
- mfspr r9,SPRG1
- std r9,PACA_EXSLB+EX_R13(r13)
- mfcr r9
- clrrdi r12,r13,32 /* get high part of &label */
- mfmsr r10
- mfspr r11,SRR0 /* save SRR0 */
- ori r12,r12,(.do_slb_miss)@l
- ori r10,r10,MSR_IR|MSR_DR /* DON'T set RI for SLB miss */
- mtspr SRR0,r12
- mfspr r12,SRR1 /* and SRR1 */
- mtspr SRR1,r10
- mfspr r3,DAR
- rfid
- b . /* prevent speculative execution */
-
- STD_EXCEPTION_PSERIES(0x400, InstructionAccess)
-
- . = 0x480
- .globl InstructionAccessSLB_Pseries
-InstructionAccessSLB_Pseries:
- HMT_MEDIUM
mtspr SPRG1,r13
- mfspr r13,SPRG3 /* get paca address into r13 */
- std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
- std r10,PACA_EXSLB+EX_R10(r13)
- std r11,PACA_EXSLB+EX_R11(r13)
- std r12,PACA_EXSLB+EX_R12(r13)
- std r3,PACASLBR3(r13)
- mfspr r9,SPRG1
- std r9,PACA_EXSLB+EX_R13(r13)
- mfcr r9
- clrrdi r12,r13,32 /* get high part of &label */
- mfmsr r10
- mfspr r11,SRR0 /* save SRR0 */
- ori r12,r12,(.do_slb_miss)@l
- ori r10,r10,MSR_IR|MSR_DR /* DON'T set RI for SLB miss */
- mtspr SRR0,r12
- mfspr r12,SRR1 /* and SRR1 */
- mtspr SRR1,r10
- mr r3,r11 /* SRR0 is faulting address */
- rfid
- b . /* prevent speculative execution */
-
- STD_EXCEPTION_PSERIES(0x500, HardwareInterrupt)
- STD_EXCEPTION_PSERIES(0x600, Alignment)
- STD_EXCEPTION_PSERIES(0x700, ProgramCheck)
- STD_EXCEPTION_PSERIES(0x800, FPUnavailable)
- STD_EXCEPTION_PSERIES(0x900, Decrementer)
- STD_EXCEPTION_PSERIES(0xa00, Trap_0a)
- STD_EXCEPTION_PSERIES(0xb00, Trap_0b)
+ mtspr SPRG2,r12
+ mfspr r13,DAR
+ mfcr r12
+ srdi r13,r13,60
+ cmpdi r13,0xc
+ beq .do_slb_bolted_Pseries
+ mtcrf 0x80,r12
+ mfspr r12,SPRG2
+ EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, DataAccessSLB_common)
+
+ STD_EXCEPTION_PSERIES( 0x400, InstructionAccess )
+ STD_EXCEPTION_PSERIES( 0x480, InstructionAccessSLB )
+ STD_EXCEPTION_PSERIES( 0x500, HardwareInterrupt )
+ STD_EXCEPTION_PSERIES( 0x600, Alignment )
+ STD_EXCEPTION_PSERIES( 0x700, ProgramCheck )
+ STD_EXCEPTION_PSERIES( 0x800, FPUnavailable )
+ STD_EXCEPTION_PSERIES( 0x900, Decrementer )
+ STD_EXCEPTION_PSERIES( 0xa00, Trap_0a )
+ STD_EXCEPTION_PSERIES( 0xb00, Trap_0b )
. = 0xc00
.globl SystemCall_Pseries
SystemCall_Pseries:
- HMT_MEDIUM
mr r9,r13
mfmsr r10
mfspr r13,SPRG3
mfspr r12,SRR1
mtspr SRR1,r10
rfid
- b . /* prevent speculative execution */
- STD_EXCEPTION_PSERIES(0xd00, SingleStep)
- STD_EXCEPTION_PSERIES(0xe00, Trap_0e)
+ STD_EXCEPTION_PSERIES( 0xd00, SingleStep )
+ STD_EXCEPTION_PSERIES( 0xe00, Trap_0e )
/* We need to deal with the Altivec unavailable exception
* here which is at 0xf20, thus in the middle of the
STD_EXCEPTION_PSERIES(0xf20, AltivecUnavailable)
- STD_EXCEPTION_PSERIES(0x1300, InstructionBreakpoint)
- STD_EXCEPTION_PSERIES(0x1700, AltivecAssist)
+ STD_EXCEPTION_PSERIES( 0x1300, InstructionBreakpoint )
+ STD_EXCEPTION_PSERIES( 0x1700, AltivecAssist )
/* moved from 0xf00 */
STD_EXCEPTION_PSERIES(0x3000, PerformanceMonitor)
-
+
. = 0x3100
_GLOBAL(do_stab_bolted_Pseries)
mtcrf 0x80,r12
mfspr r12,SPRG2
EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
+_GLOBAL(do_slb_bolted_Pseries)
+ mtcrf 0x80,r12
+ mfspr r12,SPRG2
+ EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_slb_bolted)
+
/* Space for the naca. Architected to be located at real address
* NACA_PHYS_ADDR. Various tools rely on this location being fixed.
* The first dword of the naca is required by iSeries LPAR to
* VSID generation algorithm. See include/asm/mmu_context.h.
*/
- .llong 1 /* # ESIDs to be mapped by hypervisor */
+ .llong 1 /* # ESIDs to be mapped by hypervisor */
.llong 1 /* # memory ranges to be mapped by hypervisor */
- .llong STAB0_PAGE /* Page # of segment table within load area */
- .llong 0 /* Reserved */
- .llong 0 /* Reserved */
+ .llong STAB0_PAGE /* Page # of segment table within load area */
.llong 0 /* Reserved */
+ .llong 0 /* Reserved */
+ .llong 0 /* Reserved */
.llong 0 /* Reserved */
.llong 0 /* Reserved */
.llong 0x0c00000000 /* ESID to map (Kernel at EA = 0xC000000000000000) */
- .llong 0x06a99b4b14 /* VSID to map (Kernel at VA = 0x6a99b4b140000000) */
+ .llong 0x06a99b4b14 /* VSID to map (Kernel at VA = 0x6a99b4b140000000) */
.llong 8192 /* # pages to map (32 MB) */
.llong 0 /* Offset from start of loadarea to start of map */
.llong 0x0006a99b4b140000 /* VPN of first page to map */
.globl DataAccessSLB_Iseries
DataAccessSLB_Iseries:
mtspr SPRG1,r13 /* save r13 */
- EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
- std r3,PACASLBR3(r13)
- ld r11,PACALPPACA+LPPACASRR0(r13)
- ld r12,PACALPPACA+LPPACASRR1(r13)
- mfspr r3,DAR
- b .do_slb_miss
-
- STD_EXCEPTION_ISERIES(0x400, InstructionAccess, PACA_EXGEN)
+ mtspr SPRG2,r12
+ mfspr r13,DAR
+ mfcr r12
+ srdi r13,r13,60
+ cmpdi r13,0xc
+ beq .do_slb_bolted_Iseries
+ mtcrf 0x80,r12
+ mfspr r12,SPRG2
+ EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
+ EXCEPTION_PROLOG_ISERIES_2
+ b DataAccessSLB_common
- .globl InstructionAccessSLB_Iseries
-InstructionAccessSLB_Iseries:
- mtspr SPRG1,r13 /* save r13 */
+.do_slb_bolted_Iseries:
+ mtcrf 0x80,r12
+ mfspr r12,SPRG2
EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
- std r3,PACASLBR3(r13)
- ld r11,PACALPPACA+LPPACASRR0(r13)
- ld r12,PACALPPACA+LPPACASRR1(r13)
- mr r3,r11
- b .do_slb_miss
+ EXCEPTION_PROLOG_ISERIES_2
+ b .do_slb_bolted
+ STD_EXCEPTION_ISERIES(0x400, InstructionAccess, PACA_EXGEN)
+ STD_EXCEPTION_ISERIES(0x480, InstructionAccessSLB, PACA_EXGEN)
MASKABLE_EXCEPTION_ISERIES(0x500, HardwareInterrupt)
STD_EXCEPTION_ISERIES(0x600, Alignment, PACA_EXGEN)
STD_EXCEPTION_ISERIES(0x700, ProgramCheck, PACA_EXGEN)
.globl SystemReset_Iseries
SystemReset_Iseries:
mfspr r13,SPRG3 /* Get paca address */
- mfmsr r24
- ori r24,r24,MSR_RI
- mtmsrd r24 /* RI on */
lhz r24,PACAPACAINDEX(r13) /* Get processor # */
cmpwi 0,r24,0 /* Are we processor 0? */
beq .__start_initialization_iSeries /* Start up the first processor */
rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
#else /* CONFIG_SMP */
/* Yield the processor. This is required for non-SMP kernels
- which are running on multi-threaded machines. */
+ which are running on multi-threaded machines. */
lis r3,0x8000
rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
li r11,1
stb r11,PACALPPACA+LPPACADECRINT(r13)
lwz r12,PACADEFAULTDECR(r13)
- mtspr SPRN_DEC,r12
+ mtspr DEC,r12
/* fall through */
.globl HardwareInterrupt_Iseries_masked
HardwareInterrupt_Iseries_masked:
mtcrf 0x80,r9 /* Restore regs */
- ld r11,PACALPPACA+LPPACASRR0(r13)
- ld r12,PACALPPACA+LPPACASRR1(r13)
+ ld r11,LPPACA+LPPACASRR0(r13)
+ ld r12,LPPACA+LPPACASRR1(r13)
mtspr SRR0,r11
mtspr SRR1,r12
ld r9,PACA_EXGEN+EX_R9(r13)
ld r12,PACA_EXGEN+EX_R12(r13)
ld r13,PACA_EXGEN+EX_R13(r13)
rfid
- b . /* prevent speculative execution */
#endif
/*
* Data area reserved for FWNMI option.
*/
- .= 0x7000
+ .= 0x7000
.globl fwnmi_data_area
fwnmi_data_area:
. = 0x8000
.globl SystemReset_FWNMI
SystemReset_FWNMI:
- HMT_MEDIUM
mtspr SPRG1,r13 /* save r13 */
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, SystemReset_common)
.globl MachineCheck_FWNMI
MachineCheck_FWNMI:
- HMT_MEDIUM
mtspr SPRG1,r13 /* save r13 */
EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
/*** Common interrupt handlers ***/
- STD_EXCEPTION_COMMON(0x100, SystemReset, .SystemResetException)
+ STD_EXCEPTION_COMMON( 0x100, SystemReset, .SystemResetException )
/*
* Machine check is different because we use a different
b .ret_from_except
STD_EXCEPTION_COMMON_LITE(0x900, Decrementer, .timer_interrupt)
- STD_EXCEPTION_COMMON(0xa00, Trap_0a, .UnknownException)
- STD_EXCEPTION_COMMON(0xb00, Trap_0b, .UnknownException)
- STD_EXCEPTION_COMMON(0xd00, SingleStep, .SingleStepException)
- STD_EXCEPTION_COMMON(0xe00, Trap_0e, .UnknownException)
- STD_EXCEPTION_COMMON(0xf00, PerformanceMonitor, .PerformanceMonitorException)
- STD_EXCEPTION_COMMON(0x1300, InstructionBreakpoint, .InstructionBreakpointException)
+ STD_EXCEPTION_COMMON( 0xa00, Trap_0a, .UnknownException )
+ STD_EXCEPTION_COMMON( 0xb00, Trap_0b, .UnknownException )
+ STD_EXCEPTION_COMMON( 0xd00, SingleStep, .SingleStepException )
+ STD_EXCEPTION_COMMON( 0xe00, Trap_0e, .UnknownException )
+ STD_EXCEPTION_COMMON( 0xf00, PerformanceMonitor, .PerformanceMonitorException )
+ STD_EXCEPTION_COMMON(0x1300, InstructionBreakpoint, .InstructionBreakpointException )
#ifdef CONFIG_ALTIVEC
- STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .AltivecAssistException)
+ STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .AltivecAssistException )
#else
- STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .UnknownException)
+ STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .UnknownException )
#endif
/*
* save the registers there, and call kernel_bad_stack(), which panics.
*/
bad_stack:
- ld r1,PACAEMERGSP(r13)
- subi r1,r1,64+INT_FRAME_SIZE
+ addi r1,r13,8192-64-INT_FRAME_SIZE
std r9,_CCR(r1)
std r10,GPR1(r1)
std r11,_NIP(r1)
std r10,_LINK(r1)
std r11,_CTR(r1)
std r12,_XER(r1)
- SAVE_GPR(0,r1)
+ SAVE_GPR(0, r1)
SAVE_GPR(2,r1)
SAVE_4GPRS(3,r1)
SAVE_2GPRS(7,r1)
ld r11,_NIP(r1)
andi. r3,r12,MSR_RI /* check if RI is set */
beq- unrecov_fer
- ld r3,_CCR(r1)
- ld r4,_LINK(r1)
- ld r5,_CTR(r1)
- ld r6,_XER(r1)
- mtcr r3
- mtlr r4
- mtctr r5
+ ld r3,_CCR(r1)
+ ld r4,_LINK(r1)
+ ld r5,_CTR(r1)
+ ld r6,_XER(r1)
+ mtcr r3
+ mtlr r4
+ mtctr r5
mtxer r6
REST_GPR(0, r1)
REST_8GPRS(2, r1)
mtspr SRR1,r12
mtspr SRR0,r11
REST_4GPRS(10, r1)
- ld r1,GPR1(r1)
+ ld r1,GPR1(r1)
rfid
- b . /* prevent speculative execution */
unrecov_fer:
bl .save_nvgprs
li r5,0x300
b .do_hash_page /* Try to handle as hpte fault */
+ .align 7
+ .globl DataAccessSLB_common
+DataAccessSLB_common:
+ mfspr r10,DAR
+ std r10,PACA_EXGEN+EX_DAR(r13)
+ EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
+ ld r3,PACA_EXGEN+EX_DAR(r13)
+ std r3,_DAR(r1)
+ bl .slb_allocate
+ cmpdi r3,0 /* Check return code */
+ beq fast_exception_return /* Return if we succeeded */
+ li r5,0
+ std r5,_DSISR(r1)
+ b .handle_page_fault
+
.align 7
.globl InstructionAccess_common
InstructionAccess_common:
li r5,0x400
b .do_hash_page /* Try to handle as hpte fault */
+ .align 7
+ .globl InstructionAccessSLB_common
+InstructionAccessSLB_common:
+ EXCEPTION_PROLOG_COMMON(0x480, PACA_EXGEN)
+ ld r3,_NIP(r1) /* SRR0 = NIA */
+ bl .slb_allocate
+ or. r3,r3,r3 /* Check return code */
+ beq+ fast_exception_return /* Return if we succeeded */
+
+ ld r4,_NIP(r1)
+ li r5,0
+ std r4,_DAR(r1)
+ std r5,_DSISR(r1)
+ b .handle_page_fault
+
.align 7
.globl HardwareInterrupt_common
.globl HardwareInterrupt_entry
HardwareInterrupt_entry:
DISABLE_INTS
addi r3,r1,STACK_FRAME_OVERHEAD
- bl .do_IRQ
+ bl .do_IRQ
b .ret_from_except_lite
.align 7
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS
- bl .AlignmentException
- b .ret_from_except
+ bl .AlignmentException
+ b .ret_from_except
.align 7
.globl ProgramCheck_common
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS
- bl .ProgramCheckException
- b .ret_from_except
+ bl .ProgramCheckException
+ b .ret_from_except
.align 7
.globl FPUnavailable_common
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
ENABLE_INTS
- bl .KernelFPUnavailableException
+ bl .KernelFPUnavailableException
BUG_OPCODE
.align 7
ENABLE_INTS
bl .AltivecUnavailableException
b .ret_from_except
-
+
/*
* Hash table stuff
*/
bl .local_irq_restore
b 11f
#else
- beq fast_exception_return /* Return from exception on success */
+ beq+ fast_exception_return /* Return from exception on success */
/* fall through */
#endif
andi. r11,r10,0x70
bne 1b
- /* Stick for only searching the primary group for now. */
+ /* Stick for only searching the primary group for now. */
/* At least for now, we use a very simple random castout scheme */
- /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
+ /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
mftb r11
rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
ori r11,r11,0x10
/* r10 currently points to an ste one past the group of interest */
- /* make it point to the randomly selected entry */
+ /* make it point to the randomly selected entry */
subi r10,r10,128
or r10,r10,r11 /* r10 is the entry to invalidate */
- isync /* mark the entry invalid */
+ isync /* mark the entry invalid */
ld r11,0(r10)
rldicl r11,r11,56,1 /* clear the valid bit */
rotldi r11,r11,8
ld r12,PACA_EXSLB+EX_R12(r13)
ld r13,PACA_EXSLB+EX_R13(r13)
rfid
- b . /* prevent speculative execution */
/*
* r13 points to the PACA, r9 contains the saved CR,
* r11 and r12 contain the saved SRR0 and SRR1.
- * r3 has the faulting address
* r9 - r13 are saved in paca->exslb.
- * r3 is saved in paca->slb_r3
* We assume we aren't going to take any exceptions during this procedure.
*/
-_GLOBAL(do_slb_miss)
- mflr r10
-
+/* XXX note fix masking in get_kernel_vsid to match */
+_GLOBAL(do_slb_bolted)
stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
- std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
- bl .slb_allocate /* handle it */
+ /*
+ * We take the next entry, round robin. Previously we tried
+ * to find a free slot first but that took too long. Unfortunately
+ * we dont have any LRU information to help us choose a slot.
+ */
- /* All done -- return from exception. */
+ /* r13 = paca */
+1: ld r10,PACASTABRR(r13)
+ addi r9,r10,1
+ cmpdi r9,SLB_NUM_ENTRIES
+ blt+ 2f
+ li r9,2 /* dont touch slot 0 or 1 */
+2: std r9,PACASTABRR(r13)
+
+ /* r13 = paca, r10 = entry */
+
+ /*
+ * Never cast out the segment for our kernel stack. Since we
+ * dont invalidate the ERAT we could have a valid translation
+ * for the kernel stack during the first part of exception exit
+ * which gets invalidated due to a tlbie from another cpu at a
+ * non recoverable point (after setting srr0/1) - Anton
+ */
+ slbmfee r9,r10
+ srdi r9,r9,27
+ /*
+ * Use paca->ksave as the value of the kernel stack pointer,
+ * because this is valid at all times.
+ * The >> 27 (rather than >> 28) is so that the LSB is the
+ * valid bit - this way we check valid and ESID in one compare.
+ * In order to completely close the tiny race in the context
+ * switch (between updating r1 and updating paca->ksave),
+ * we check against both r1 and paca->ksave.
+ */
+ srdi r11,r1,27
+ ori r11,r11,1
+ cmpd r11,r9
+ beq- 1b
+ ld r11,PACAKSAVE(r13)
+ srdi r11,r11,27
+ ori r11,r11,1
+ cmpd r11,r9
+ beq- 1b
+
+ /* r13 = paca, r10 = entry */
+
+ /* (((ea >> 28) & 0x1fff) << 15) | (ea >> 60) */
+ mfspr r9,DAR
+ rldicl r11,r9,36,51
+ sldi r11,r11,15
+ srdi r9,r9,60
+ or r11,r11,r9
+
+ /* VSID_RANDOMIZER */
+ li r9,9
+ sldi r9,r9,32
+ oris r9,r9,58231
+ ori r9,r9,39831
+
+ /* vsid = (ordinal * VSID_RANDOMIZER) & VSID_MASK */
+ mulld r11,r11,r9
+ clrldi r11,r11,28
+
+ /* r13 = paca, r10 = entry, r11 = vsid */
+
+ /* Put together slb word1 */
+ sldi r11,r11,12
+
+BEGIN_FTR_SECTION
+ /* set kp and c bits */
+ ori r11,r11,0x480
+END_FTR_SECTION_IFCLR(CPU_FTR_16M_PAGE)
+BEGIN_FTR_SECTION
+ /* set kp, l and c bits */
+ ori r11,r11,0x580
+END_FTR_SECTION_IFSET(CPU_FTR_16M_PAGE)
+
+ /* r13 = paca, r10 = entry, r11 = slb word1 */
- ld r10,PACA_EXSLB+EX_LR(r13)
- ld r3,PACASLBR3(r13)
+ /* Put together slb word0 */
+ mfspr r9,DAR
+ clrrdi r9,r9,28 /* get the new esid */
+ oris r9,r9,0x800 /* set valid bit */
+ rldimi r9,r10,0,52 /* insert entry */
+
+ /* r13 = paca, r9 = slb word0, r11 = slb word1 */
+
+ /*
+ * No need for an isync before or after this slbmte. The exception
+ * we enter with and the rfid we exit with are context synchronizing .
+ */
+ slbmte r11,r9
+
+ /* All done -- return from exception. */
lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
- mtlr r10
-
andi. r10,r12,MSR_RI /* check for unrecoverable exception */
beq- unrecov_slb
-.machine push
-.machine "power4"
+ /*
+ * Until everyone updates binutils hardwire the POWER4 optimised
+ * single field mtcrf
+ */
+#if 0
+ .machine push
+ .machine "power4"
mtcrf 0x80,r9
- mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
-.machine pop
+ .machine pop
+#else
+ .long 0x7d380120
+#endif
+
+ mfmsr r10
+ clrrdi r10,r10,2
+ mtmsrd r10,1
mtspr SRR0,r11
mtspr SRR1,r12
ld r12,PACA_EXSLB+EX_R12(r13)
ld r13,PACA_EXSLB+EX_R13(r13)
rfid
- b . /* prevent speculative execution */
unrecov_slb:
EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
isync
/* Set up a paca value for this processor. */
- LOADADDR(r24, paca) /* Get base vaddr of paca array */
- mulli r13,r3,PACA_SIZE /* Calculate vaddr of right paca */
- add r13,r13,r24 /* for this processor. */
+ LOADADDR(r24, paca) /* Get base vaddr of paca array */
+ mulli r13,r3,PACA_SIZE /* Calculate vaddr of right paca */
+ add r13,r13,r24 /* for this processor. */
- mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
- mr r24,r3 /* __secondary_start needs cpu# */
+ mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
+ mr r24,r3 /* __secondary_start needs cpu# */
1:
HMT_LOW
- lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
- /* start. */
+ lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
+ /* start. */
sync
- /* Create a temp kernel stack for use before relocation is on. */
- ld r1,PACAEMERGSP(r13)
- subi r1,r1,STACK_FRAME_OVERHEAD
+ /* Create a temp kernel stack for use before relocation is on. */
+ mr r1,r13
+ addi r1,r1,PACAGUARD
+ addi r1,r1,0x1000
+ subi r1,r1,STACK_FRAME_OVERHEAD
cmpwi 0,r23,0
#ifdef CONFIG_SMP
bne .__secondary_start
#endif
#endif
- b 1b /* Loop until told to go */
+ b 1b /* Loop until told to go */
#ifdef CONFIG_PPC_ISERIES
_GLOBAL(__start_initialization_iSeries)
/* Clear out the BSS */
LOADADDR(r8,__bss_start)
- sub r11,r11,r8 /* bss size */
- addi r11,r11,7 /* round up to an even double word */
- rldicl. r11,r11,61,3 /* shift right by 3 */
+ sub r11,r11,r8 /* bss size */
+ addi r11,r11,7 /* round up to an even double word */
+ rldicl. r11,r11,61,3 /* shift right by 3 */
beq 4f
addi r8,r8,-8
li r0,0
- mtctr r11 /* zero this many doublewords */
+ mtctr r11 /* zero this many doublewords */
3: stdu r0,8(r8)
bdnz 3b
4:
std r4,0(r9) /* set the naca pointer */
/* Get the pointer to the segment table */
- ld r6,PACA(r4) /* Get the base paca pointer */
+ ld r6,PACA(r4) /* Get the base paca pointer */
ld r4,PACASTABVIRT(r6)
- bl .iSeries_fixup_klimit
+ bl .iSeries_fixup_klimit
/* relocation is on at this point */
mtspr SRR1,r3
sync
rfid
- b . /* prevent speculative execution */
_GLOBAL(__start_initialization_pSeries)
mr r31,r3 /* save parameters */
mr r30,r4
bl .reloc_offset
LOADADDR(r2,__toc_start)
- addi r2,r2,0x4000
- addi r2,r2,0x4000
+ addi r2,r2,0x4000
+ addi r2,r2,0x4000
/* Relocate the TOC from a virt addr to a real addr */
sub r2,r2,r3
* unknown exception placeholders.
*
* Note: This process overwrites the OF exception vectors.
- * r26 == relocation offset
- * r27 == KERNELBASE
+ * r26 == relocation offset
+ * r27 == KERNELBASE
*/
bl .reloc_offset
mr r26,r3
SET_REG_TO_CONST(r27,KERNELBASE)
- li r3,0 /* target addr */
+ li r3,0 /* target addr */
// XXX FIXME: Use phys returned by OF (r23)
- sub r4,r27,r26 /* source addr */
- /* current address of _start */
- /* i.e. where we are running */
- /* the source addr */
+ sub r4,r27,r26 /* source addr */
+ /* current address of _start */
+ /* i.e. where we are running */
+ /* the source addr */
- LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
+ LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
sub r5,r5,r27
- li r6,0x100 /* Start offset, the first 0x100 */
- /* bytes were copied earlier. */
+ li r6,0x100 /* Start offset, the first 0x100 */
+ /* bytes were copied earlier. */
- bl .copy_and_flush /* copy the first n bytes */
- /* this includes the code being */
- /* executed here. */
+ bl .copy_and_flush /* copy the first n bytes */
+ /* this includes the code being */
+ /* executed here. */
- LOADADDR(r0, 4f) /* Jump to the copy of this code */
- mtctr r0 /* that we just made/relocated */
+ LOADADDR(r0, 4f) /* Jump to the copy of this code */
+ mtctr r0 /* that we just made/relocated */
bctr
4: LOADADDR(r5,klimit)
_GLOBAL(copy_and_flush)
addi r5,r5,-8
addi r6,r6,-8
-4: li r0,16 /* Use the least common */
- /* denominator cache line */
- /* size. This results in */
- /* extra cache line flushes */
- /* but operation is correct. */
- /* Can't get cache line size */
- /* from NACA as it is being */
- /* moved too. */
-
- mtctr r0 /* put # words/line in ctr */
-3: addi r6,r6,8 /* copy a cache line */
+4: li r0,16 /* Use the least common */
+ /* denominator cache line */
+ /* size. This results in */
+ /* extra cache line flushes */
+ /* but operation is correct. */
+ /* Can't get cache line size */
+ /* from NACA as it is being */
+ /* moved too. */
+
+ mtctr r0 /* put # words/line in ctr */
+3: addi r6,r6,8 /* copy a cache line */
ldx r0,r6,r4
stdx r0,r6,r3
bdnz 3b
- dcbst r6,r3 /* write it to memory */
+ dcbst r6,r3 /* write it to memory */
sync
- icbi r6,r3 /* flush the icache line */
+ icbi r6,r3 /* flush the icache line */
cmpld 0,r6,r5
blt 4b
sync
* On entry: r13 == 'current' && last_task_used_math != 'current'
*/
_STATIC(load_up_fpu)
- mfmsr r5 /* grab the current MSR */
+ mfmsr r5 /* grab the current MSR */
ori r5,r5,MSR_FP
- mtmsrd r5 /* enable use of fpu now */
+ mtmsrd r5 /* enable use of fpu now */
isync
/*
* For SMP, we don't do lazy FPU switching because it just gets too
* Disable the FPU.
*/
_GLOBAL(disable_kernel_fp)
- mfmsr r3
- rldicl r0,r3,(63-MSR_FP_LG),1
- rldicl r3,r0,(MSR_FP_LG+1),0
- mtmsrd r3 /* disable use of fpu now */
+ mfmsr r3
+ rldicl r0,r3,(63-MSR_FP_LG),1
+ rldicl r3,r0,(MSR_FP_LG+1),0
+ mtmsrd r3 /* disable use of fpu now */
isync
blr
* On entry: r13 == 'current' && last_task_used_altivec != 'current'
*/
_STATIC(load_up_altivec)
- mfmsr r5 /* grab the current MSR */
+ mfmsr r5 /* grab the current MSR */
oris r5,r5,MSR_VEC@h
- mtmsrd r5 /* enable use of VMX now */
+ mtmsrd r5 /* enable use of VMX now */
isync
/*
* Disable the VMX.
*/
_GLOBAL(disable_kernel_altivec)
- mfmsr r3
- rldicl r0,r3,(63-MSR_VEC_LG),1
- rldicl r3,r0,(MSR_VEC_LG+1),0
- mtmsrd r3 /* disable use of VMX now */
+ mfmsr r3
+ rldicl r0,r3,(63-MSR_VEC_LG),1
+ rldicl r3,r0,(MSR_VEC_LG+1),0
+ mtmsrd r3 /* disable use of VMX now */
isync
blr
mtmsrd r3 /* RI on */
/* Set up a paca value for this processor. */
- LOADADDR(r4, paca) /* Get base vaddr of paca array */
+ LOADADDR(r4, paca) /* Get base vaddr of paca array */
mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
- add r13,r13,r4 /* for this processor. */
- mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
+ add r13,r13,r4 /* for this processor. */
+ mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
- /* Create a temp kernel stack for use before relocation is on. */
- ld r1,PACAEMERGSP(r13)
- subi r1,r1,STACK_FRAME_OVERHEAD
+ /* Create a temp kernel stack for use before relocation is on. */
+ mr r1,r13
+ addi r1,r1,PACAGUARD
+ addi r1,r1,0x1000
+ subi r1,r1,STACK_FRAME_OVERHEAD
b .__secondary_start
* 1. Processor number
* 2. Segment table pointer (virtual address)
* On entry the following are set:
- * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
+ * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
* r24 = cpu# (in Linux terms)
* r13 = paca virtual address
* SPRG3 = paca virtual address
HMT_MEDIUM /* Set thread priority to MEDIUM */
- ld r2,PACATOC(r13)
+ /* set up the TOC (virtual address) */
+ LOADADDR(r2,__toc_start)
+ addi r2,r2,0x4000
+ addi r2,r2,0x4000
+
+ std r2,PACATOC(r13)
li r6,0
stb r6,PACAPROCENABLED(r13)
#ifndef CONFIG_PPC_ISERIES
/* Initialize the page table pointer register. */
LOADADDR(r6,_SDR1)
- ld r6,0(r6) /* get the value of _SDR1 */
- mtspr SDR1,r6 /* set the htab location */
+ ld r6,0(r6) /* get the value of _SDR1 */
+ mtspr SDR1,r6 /* set the htab location */
#endif
- /* Initialize the first segment table (or SLB) entry */
- ld r3,PACASTABVIRT(r13) /* get addr of segment table */
+ /* Initialize the first segment table (or SLB) entry */
+ ld r3,PACASTABVIRT(r13) /* get addr of segment table */
bl .stab_initialize
- /* Initialize the kernel stack. Just a repeat for iSeries. */
+ /* Initialize the kernel stack. Just a repeat for iSeries. */
LOADADDR(r3,current_set)
- sldi r28,r24,3 /* get current_set[cpu#] */
+ sldi r28,r24,3 /* get current_set[cpu#] */
ldx r1,r3,r28
addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
+ li r0,0
+ std r0,0(r1)
std r1,PACAKSAVE(r13)
- ld r3,PACASTABREAL(r13) /* get raddr of segment table */
- ori r4,r3,1 /* turn on valid bit */
+ ld r3,PACASTABREAL(r13) /* get raddr of segment table */
+ ori r4,r3,1 /* turn on valid bit */
#ifdef CONFIG_PPC_ISERIES
li r0,-1 /* hypervisor call */
sc /* HvCall_setASR */
#else
/* set the ASR */
- li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
- lwz r3,PLATFORM(r3) /* r3 = platform flags */
+ li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
+ lwz r3,PLATFORM(r3) /* r3 = platform flags */
cmpldi r3,PLATFORM_PSERIES_LPAR
- bne 98f
+ bne 98f
mfspr r3,PVR
srwi r3,r3,16
- cmpwi r3,0x37 /* SStar */
+ cmpwi r3,0x37 /* SStar */
beq 97f
- cmpwi r3,0x36 /* IStar */
+ cmpwi r3,0x36 /* IStar */
beq 97f
- cmpwi r3,0x34 /* Pulsar */
+ cmpwi r3,0x34 /* Pulsar */
bne 98f
-97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
- HVSC /* Invoking hcall */
+97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
+ HVSC /* Invoking hcall */
b 99f
-98: /* !(rpa hypervisor) || !(star) */
- mtasr r4 /* set the stab location */
+98: /* !(rpa hypervisor) || !(star) */
+ mtasr r4 /* set the stab location */
99:
#endif
li r7,0
mtspr SRR0,r3
mtspr SRR1,r4
rfid
- b . /* prevent speculative execution */
/*
* Running with relocation on at this point. All we want to do is
*/
_GLOBAL(start_secondary_prolog)
li r3,0
- std r3,0(r1) /* Zero the stack frame pointer */
+ std r3,0(r1) /* Zero the stack frame pointer */
bl .start_secondary
#endif
* This subroutine clobbers r11 and r12
*/
_GLOBAL(enable_64b_mode)
- mfmsr r11 /* grab the current MSR */
- li r12,1
- rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
- or r11,r11,r12
- li r12,1
- rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
- or r11,r11,r12
- mtmsrd r11
+ mfmsr r11 /* grab the current MSR */
+ li r12,1
+ rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
+ or r11,r11,r12
+ li r12,1
+ rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
+ or r11,r11,r12
+ mtmsrd r11
isync
blr
ori r6,r6,MSR_RI
mtmsrd r6 /* RI on */
- /* setup the systemcfg pointer which is needed by *tab_initialize */
+ /* setup the systemcfg pointer which is needed by *tab_initialize */
LOADADDR(r6,systemcfg)
- sub r6,r6,r26 /* addr of the variable systemcfg */
+ sub r6,r6,r26 /* addr of the variable systemcfg */
li r27,SYSTEMCFG_PHYS_ADDR
- std r27,0(r6) /* set the value of systemcfg */
+ std r27,0(r6) /* set the value of systemcfg */
- /* setup the naca pointer which is needed by *tab_initialize */
+ /* setup the naca pointer which is needed by *tab_initialize */
LOADADDR(r6,naca)
- sub r6,r6,r26 /* addr of the variable naca */
+ sub r6,r6,r26 /* addr of the variable naca */
li r27,NACA_PHYS_ADDR
- std r27,0(r6) /* set the value of naca */
+ std r27,0(r6) /* set the value of naca */
#ifdef CONFIG_HMT
/* Start up the second thread on cpu 0 */
mfspr r3,PVR
srwi r3,r3,16
- cmpwi r3,0x34 /* Pulsar */
+ cmpwi r3,0x34 /* Pulsar */
beq 90f
- cmpwi r3,0x36 /* Icestar */
+ cmpwi r3,0x36 /* Icestar */
beq 90f
- cmpwi r3,0x37 /* SStar */
+ cmpwi r3,0x37 /* SStar */
beq 90f
- b 91f /* HMT not supported */
-90: li r3,0
+ b 91f /* HMT not supported */
+90: li r3,0
bl .hmt_start_secondary
91:
#endif
li r3,1
LOADADDR(r5,__secondary_hold_spinloop)
tophys(r4,r5)
- std r3,0(r4)
+ std r3,0(r4)
#endif
/* The following gets the stack and TOC set up with the regs */
/* set up the TOC (physical address) */
LOADADDR(r2,__toc_start)
- addi r2,r2,0x4000
- addi r2,r2,0x4000
+ addi r2,r2,0x4000
+ addi r2,r2,0x4000
sub r2,r2,r26
LOADADDR(r3,cpu_specs)
mr r5,r26
bl .identify_cpu
- /* Get the pointer to the segment table which is used by */
- /* stab_initialize */
+ /* Get the pointer to the segment table which is used by */
+ /* stab_initialize */
LOADADDR(r27, boot_cpuid)
sub r27,r27,r26
lwz r27,0(r27)
- LOADADDR(r24, paca) /* Get base vaddr of paca array */
- mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
- add r13,r13,r24 /* for this processor. */
- sub r13,r13,r26 /* convert to physical addr */
+ LOADADDR(r24, paca) /* Get base vaddr of paca array */
+ mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
+ add r13,r13,r24 /* for this processor. */
+ sub r13,r13,r26 /* convert to physical addr */
mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */
ld r3,PACASTABREAL(r13)
- ori r4,r3,1 /* turn on valid bit */
+ ori r4,r3,1 /* turn on valid bit */
/* set the ASR */
li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
- lwz r3,PLATFORM(r3) /* r3 = platform flags */
+ lwz r3,PLATFORM(r3) /* r3 = platform flags */
cmpldi r3,PLATFORM_PSERIES_LPAR
- bne 98f
+ bne 98f
mfspr r3,PVR
srwi r3,r3,16
- cmpwi r3,0x37 /* SStar */
+ cmpwi r3,0x37 /* SStar */
beq 97f
- cmpwi r3,0x36 /* IStar */
+ cmpwi r3,0x36 /* IStar */
beq 97f
- cmpwi r3,0x34 /* Pulsar */
+ cmpwi r3,0x34 /* Pulsar */
bne 98f
-97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
- HVSC /* Invoking hcall */
- b 99f
-98: /* !(rpa hypervisor) || !(star) */
- mtasr r4 /* set the stab location */
+97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
+ HVSC /* Invoking hcall */
+ b 99f
+98: /* !(rpa hypervisor) || !(star) */
+ mtasr r4 /* set the stab location */
99:
mfspr r6,SPRG3
- ld r3,PACASTABREAL(r6) /* restore r3 for stab_initialize */
+ ld r3,PACASTABREAL(r6) /* restore r3 for stab_initialize */
- /* Initialize an initial memory mapping and turn on relocation. */
+ /* Initialize an initial memory mapping and turn on relocation. */
bl .stab_initialize
bl .htab_initialize
lwz r3,PLATFORM(r3) /* r3 = platform flags */
/* Test if bit 0 is set (LPAR bit) */
andi. r3,r3,0x1
- bne 98f
+ bne 98f
LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
sub r6,r6,r26
ld r6,0(r6) /* get the value of _SDR1 */
mtspr SRR0,r3
mtspr SRR1,r4
rfid
- b . /* prevent speculative execution */
#endif /* CONFIG_PPC_PSERIES */
/* This is where all platforms converge execution */
li r0,0
stdu r0,-STACK_FRAME_OVERHEAD(r1)
+ /* set up the TOC */
+ LOADADDR(r2,__toc_start)
+ addi r2,r2,0x4000
+ addi r2,r2,0x4000
+
/* Apply the CPUs-specific fixups (nop out sections not relevant
* to this CPU
*/
/* setup the naca pointer */
LOADADDR(r9,naca)
SET_REG_TO_CONST(r8, NACA_VIRT_ADDR)
- std r8,0(r9) /* set the value of the naca ptr */
+ std r8,0(r9) /* set the value of the naca ptr */
LOADADDR(r26, boot_cpuid)
lwz r26,0(r26)
- LOADADDR(r24, paca) /* Get base vaddr of paca array */
- mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
- add r13,r13,r24 /* for this processor. */
+ LOADADDR(r24, paca) /* Get base vaddr of paca array */
+ mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
+ add r13,r13,r24 /* for this processor. */
mtspr SPRG3,r13
/* ptr to current */
LOADADDR(r4,init_task)
std r4,PACACURRENT(r13)
- /* Load the TOC */
- ld r2,PACATOC(r13)
+ std r2,PACATOC(r13)
std r1,PACAKSAVE(r13)
/* Restore the parms passed in from the bootloader. */
LOADADDR(r5, hmt_thread_data)
mfspr r7,PVR
srwi r7,r7,16
- cmpwi r7,0x34 /* Pulsar */
+ cmpwi r7,0x34 /* Pulsar */
beq 90f
- cmpwi r7,0x36 /* Icestar */
+ cmpwi r7,0x36 /* Icestar */
beq 91f
- cmpwi r7,0x37 /* SStar */
+ cmpwi r7,0x37 /* SStar */
beq 91f
b 101f
90: mfspr r6,PIR
104: addi r7,r7,4
lwzx r9,r5,r7
- mr r24,r9
+ mr r24,r9
101:
#endif
- mr r3,r24
- b .pseries_secondary_smp_init
+ mr r3,r24
+ b .pseries_secondary_smp_init
#ifdef CONFIG_HMT
_GLOBAL(hmt_start_secondary)
LOADADDR(r4,__hmt_secondary_hold)
clrldi r4,r4,4
- mtspr NIADORM, r4
- mfspr r4, MSRDORM
- li r5, -65
- and r4, r4, r5
- mtspr MSRDORM, r4
+ mtspr NIADORM, r4
+ mfspr r4, MSRDORM
+ li r5, -65
+ and r4, r4, r5
+ mtspr MSRDORM, r4
lis r4,0xffef
ori r4,r4,0x7403
mtspr TSC, r4
li r4,0x1f4
mtspr TST, r4
- mfspr r4, HID0
- ori r4, r4, 0x1
- mtspr HID0, r4
- mfspr r4, CTRLF
- oris r4, r4, 0x40
- mtspr CTRLT, r4
+ mfspr r4, HID0
+ ori r4, r4, 0x1
+ mtspr HID0, r4
+ mfspr r4, CTRLF
+ oris r4, r4, 0x40
+ mtspr CTRLT, r4
blr
#endif
* which is page-aligned.
*/
.data
- .align 12
+ .align 12
.globl sdata
sdata:
.globl empty_zero_page
/* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */
.globl stab_array
stab_array:
- .space 4096 * 48
+ .space 4096 * 48
/*
* This space gets a copy of optional info passed to us by the bootstrap
*/
.globl cmd_line
cmd_line:
- .space COMMAND_LINE_SIZE
+ .space 512 /* COMMAND_LINE_SIZE */
git://git.onelab.eu / linux-2.6.git / blobdiff