#define SECONDARY_PROCESSORS
#include <linux/config.h>
-#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/mmu.h>
/*
* On pSeries, secondary processors spin in the following code.
- * At entry, r3 = this processor's number (physical cpu id)
+ * At entry, r3 = this processor's number (in Linux terms, not hardware).
*/
_GLOBAL(pseries_secondary_smp_init)
- mr r24,r3
-
/* turn on 64-bit mode */
bl .enable_64b_mode
isync
- /* Copy some CPU settings from CPU 0 */
- bl .__restore_cpu_setup
+ /* Set up a paca value for this processor. */
+ LOADADDR(r24, paca) /* Get base vaddr of paca array */
+ mulli r13,r3,PACA_SIZE /* Calculate vaddr of right paca */
+ add r13,r13,r24 /* for this processor. */
- /* Set up a paca value for this processor. Since we have the
- * physical cpu id in r3, we need to search the pacas to find
- * which logical id maps to our physical one.
- */
- LOADADDR(r13, paca) /* Get base vaddr of paca array */
- li r5,0 /* logical cpu id */
-1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
- cmpw r6,r24 /* Compare to our id */
- beq 2f
- addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
- addi r5,r5,1
- cmpwi r5,NR_CPUS
- blt 1b
-
-99: HMT_LOW /* Couldn't find our CPU id */
- b 99b
-
-2: mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
- /* From now on, r24 is expected to be logica cpuid */
- mr r24,r5
-3: HMT_LOW
+ mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
+ mr r24,r3 /* __secondary_start needs cpu# */
+
+1:
+ HMT_LOW
lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
/* start. */
sync
bne .__secondary_start
#endif
#endif
- b 3b /* Loop until told to go */
+ b 1b /* Loop until told to go */
#ifdef CONFIG_PPC_ISERIES
_STATIC(__start_initialization_iSeries)
/* Clear out the BSS */
91:
#endif
+#ifdef CONFIG_SMP
+ /* All secondary cpus are now spinning on a common
+ * spinloop, release them all now so they can start
+ * to spin on their individual paca spinloops.
+ * For non SMP kernels, the secondary cpus never
+ * get out of the common spinloop.
+ */
+ li r3,1
+ LOADADDR(r5,__secondary_hold_spinloop)
+ tophys(r4,r5)
+ std r3,0(r4)
+#endif
+
/* The following gets the stack and TOC set up with the regs */
/* pointing to the real addr of the kernel stack. This is */
/* all done to support the C function call below which sets */
li r0,0
stdu r0,-STACK_FRAME_OVERHEAD(r1)
- /* set up the TOC (physical address) */
+ /* set up the TOC (physical address) */
LOADADDR(r2,__toc_start)
addi r2,r2,0x4000
addi r2,r2,0x4000
mr r5,r26
bl .identify_cpu
- /* Save some low level config HIDs of CPU0 to be copied to
- * other CPUs later on, or used for suspend/resume
- */
- bl .__save_cpu_setup
- sync
-
/* Setup a valid physical PACA pointer in SPRG3 for early_setup
* note that boot_cpuid can always be 0 nowadays since there is
* nowhere it can be initialized differently before we reach this
blr
#endif
-#if defined(CONFIG_SMP) && !defined(CONFIG_PPC_ISERIES)
-_GLOBAL(smp_release_cpus)
- /* All secondary cpus are spinning on a common
- * spinloop, release them all now so they can start
- * to spin on their individual paca spinloops.
- * For non SMP kernels, the secondary cpus never
- * get out of the common spinloop.
- */
- li r3,1
- LOADADDR(r5,__secondary_hold_spinloop)
- std r3,0(r5)
- sync
- blr
-#endif /* CONFIG_SMP && !CONFIG_PPC_ISERIES */
-
-
/*
* We put a few things here that have to be page-aligned.
* This stuff goes at the beginning of the data segment,