* CPU init code
*
* Copyright (C) 2002, 2003 Paul Mundt
+ * Copyright (C) 2003 Richard Curnow
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
#include <linux/kernel.h>
#include <asm/processor.h>
#include <asm/uaccess.h>
+#include <asm/page.h>
#include <asm/system.h>
#include <asm/cacheflush.h>
#include <asm/cache.h>
* Generic wrapper for command line arguments to disable on-chip
* peripherals (nofpu, nodsp, and so forth).
*/
-#define onchip_setup(x) \
-static int x##_disabled __initdata = 0; \
+#define onchip_setup(x) \
+static int x##_disabled __initdata = 0; \
\
static int __init x##_setup(char *opts) \
{ \
x##_disabled = 1; \
- return 0; \
+ return 1; \
} \
__setup("no" __stringify(x), x##_setup);
ccr = ctrl_inl(CCR);
/*
- * If the cache is already enabled .. flush it.
+ * At this point we don't know whether the cache is enabled or not - a
+ * bootloader may have enabled it. There are at least 2 things that
+ * could be dirty in the cache at this point:
+ * 1. kernel command line set up by boot loader
+ * 2. spilled registers from the prolog of this function
+ * => before re-initialising the cache, we must do a purge of the whole
+ * cache out to memory for safety. As long as nothing is spilled
+ * during the loop to lines that have already been done, this is safe.
+ * - RPC
*/
if (ccr & CCR_CACHE_ENABLE) {
unsigned long ways, waysize, addrstart;
waysize = cpu_data->dcache.sets;
+#ifdef CCR_CACHE_ORA
/*
* If the OC is already in RAM mode, we only have
* half of the entries to flush..
*/
if (ccr & CCR_CACHE_ORA)
waysize >>= 1;
+#endif
waysize <<= cpu_data->dcache.entry_shift;
} while (--ways);
}
- /*
+ /*
* Default CCR values .. enable the caches
* and invalidate them immediately..
*/
/* Force EMODE if possible */
if (cpu_data->dcache.ways > 1)
flags |= CCR_CACHE_EMODE;
+ else
+ flags &= ~CCR_CACHE_EMODE;
#endif
#ifdef CONFIG_SH_WRITETHROUGH
/* Turn on OCRAM -- halve the OC */
flags |= CCR_CACHE_ORA;
cpu_data->dcache.sets >>= 1;
+
+ cpu_data->dcache.way_size = cpu_data->dcache.sets *
+ cpu_data->dcache.linesz;
#endif
ctrl_outl(flags, CCR);
}
#endif /* CONFIG_SH_DSP */
-/*
+/**
* sh_cpu_init
*
* This is our initial entry point for each CPU, and is invoked on the boot
/* Init the cache */
cache_init();
+ shm_align_mask = max_t(unsigned long,
+ cpu_data->dcache.way_size - 1,
+ PAGE_SIZE - 1);
+
/* Disable the FPU */
if (fpu_disabled) {
printk("FPU Disabled\n");
/* FPU initialization */
if ((cpu_data->flags & CPU_HAS_FPU)) {
clear_thread_flag(TIF_USEDFPU);
- current->used_math = 0;
+ clear_used_math();
}
#ifdef CONFIG_SH_DSP
/* Probe for DSP */
dsp_init();
-
+
/* Disable the DSP */
if (dsp_disabled) {
printk("DSP Disabled\n");