* for more details.
*
*/
-
#include <linux/init.h>
#include <linux/mman.h>
#include <linux/mm.h>
#include <asm/mmu_context.h>
#include <asm/cacheflush.h>
-/* The 32KB cache on the SH7705 suffers from the same synonym problem
- * as SH4 CPUs */
-
-#define __pte_offset(address) \
- ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset(dir, address) ((pte_t *) pmd_page_kernel(*(dir)) + \
- __pte_offset(address))
-
+/*
+ * The 32KB cache on the SH7705 suffers from the same synonym problem
+ * as SH4 CPUs
+ */
static inline void cache_wback_all(void)
{
unsigned long ways, waysize, addrstart;
__flush_wback_region((void *)start, end - start);
}
-
/*
* Writeback&Invalidate the D-cache of the page
*/
local_irq_restore(flags);
}
-
/*
* Write back & invalidate the D-cache of the page.
* (To avoid "alias" issues)
*
* ADDRESS: Virtual Address (U0 address)
*/
-void flush_cache_page(struct vm_area_struct *vma, unsigned long address)
+void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
+ unsigned long pfn)
{
- pgd_t *dir;
- pmd_t *pmd;
- pte_t *pte;
- pte_t entry;
- unsigned long phys;
-
- dir = pgd_offset(vma->vm_mm, address);
- pmd = pmd_offset(dir, address);
- if (pmd_none(*pmd) || pmd_bad(*pmd))
- return;
- pte = pte_offset(pmd, address);
- entry = *pte;
- if (pte_none(entry) || !pte_present(entry))
- return;
-
- phys = pte_val(entry)&PTE_PHYS_MASK;
- __flush_dcache_page(phys);
+ __flush_dcache_page(pfn << PAGE_SHIFT);
}
/*
{
__flush_purge_region(page_address(page), PAGE_SIZE);
}
-