linux 2.6.16.38 w/ vs2.0.3-rc1

[linux-2.6.git] / arch / sparc64 / kernel / devices.c

diff --git a/arch/sparc64/kernel/devices.c b/arch/sparc64/kernel/devices.c
index 559b6d7..df9a1ca 100644 (file)
--- a/arch/sparc64/kernel/devices.c
+++ b/arch/sparc64/kernel/devices.c
@@ -24,7 +24,7 @@
 /* Used to synchronize acceses to NatSemi SUPER I/O chip configure
  * operations in asm/ns87303.h
  */
-spinlock_t ns87303_lock = SPIN_LOCK_UNLOCKED;
+DEFINE_SPINLOCK(ns87303_lock);
 
 extern void cpu_probe(void);
 extern void central_probe(void);
@@ -135,6 +135,28 @@ void __init device_scan(void)
                cpu_data(0).clock_tick = prom_getintdefault(cpu_node,
                                                            "clock-frequency",
                                                            0);
+               cpu_data(0).dcache_size = prom_getintdefault(cpu_node,
+                                                            "dcache-size",
+                                                            16 * 1024);
+               cpu_data(0).dcache_line_size =
+                       prom_getintdefault(cpu_node, "dcache-line-size", 32);
+               cpu_data(0).icache_size = prom_getintdefault(cpu_node,
+                                                            "icache-size",
+                                                            16 * 1024);
+               cpu_data(0).icache_line_size =
+                       prom_getintdefault(cpu_node, "icache-line-size", 32);
+               cpu_data(0).ecache_size = prom_getintdefault(cpu_node,
+                                                            "ecache-size",
+                                                            4 * 1024 * 1024);
+               cpu_data(0).ecache_line_size =
+                       prom_getintdefault(cpu_node, "ecache-line-size", 64);
+               printk("CPU[0]: Caches "
+                      "D[sz(%d):line_sz(%d)] "
+                      "I[sz(%d):line_sz(%d)] "
+                      "E[sz(%d):line_sz(%d)]\n",
+                      cpu_data(0).dcache_size, cpu_data(0).dcache_line_size,
+                      cpu_data(0).icache_size, cpu_data(0).icache_line_size,
+                      cpu_data(0).ecache_size, cpu_data(0).ecache_line_size);
        }
 #endif