#include <asm/sections.h>
#include <asm/cpudata.h>
-spinlock_t mostek_lock = SPIN_LOCK_UNLOCKED;
-spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED;
-unsigned long mstk48t02_regs = 0UL;
+DEFINE_SPINLOCK(mostek_lock);
+DEFINE_SPINLOCK(rtc_lock);
+void __iomem *mstk48t02_regs = NULL;
#ifdef CONFIG_PCI
unsigned long ds1287_regs = 0UL;
#endif
extern unsigned long wall_jiffies;
-u64 jiffies_64 = INITIAL_JIFFIES;
-
-EXPORT_SYMBOL(jiffies_64);
-
-static unsigned long mstk48t08_regs = 0UL;
-static unsigned long mstk48t59_regs = 0UL;
+static void __iomem *mstk48t08_regs;
+static void __iomem *mstk48t59_regs;
static int set_rtc_mmss(unsigned long);
-struct sparc64_tick_ops *tick_ops;
-
#define TICK_PRIV_BIT (1UL << 63)
#ifdef CONFIG_SMP
return new_tick;
}
-static struct sparc64_tick_ops tick_operations = {
+static struct sparc64_tick_ops tick_operations __read_mostly = {
.init_tick = tick_init_tick,
.get_tick = tick_get_tick,
.get_compare = tick_get_compare,
.softint_mask = 1UL << 0,
};
+struct sparc64_tick_ops *tick_ops __read_mostly = &tick_operations;
+
static void stick_init_tick(unsigned long offset)
{
tick_disable_protection();
return new_compare;
}
-static struct sparc64_tick_ops stick_operations = {
+static struct sparc64_tick_ops stick_operations __read_mostly = {
.init_tick = stick_init_tick,
.get_tick = stick_get_tick,
.get_compare = stick_get_compare,
* Since STICK is constantly updating, we have to access it carefully.
*
* The sequence we use to read is:
- * 1) read low
- * 2) read high
- * 3) read low again, if it rolled over increment high by 1
+ * 1) read high
+ * 2) read low
+ * 3) read high again, if it rolled re-read both low and high again.
*
* Writing STICK safely is also tricky:
* 1) write low to zero
static unsigned long __hbird_read_stick(void)
{
unsigned long ret, tmp1, tmp2, tmp3;
- unsigned long addr = HBIRD_STICK_ADDR;
+ unsigned long addr = HBIRD_STICK_ADDR+8;
- __asm__ __volatile__("ldxa [%1] %5, %2\n\t"
- "add %1, 0x8, %1\n\t"
- "ldxa [%1] %5, %3\n\t"
+ __asm__ __volatile__("ldxa [%1] %5, %2\n"
+ "1:\n\t"
"sub %1, 0x8, %1\n\t"
+ "ldxa [%1] %5, %3\n\t"
+ "add %1, 0x8, %1\n\t"
"ldxa [%1] %5, %4\n\t"
"cmp %4, %2\n\t"
- "blu,a,pn %%xcc, 1f\n\t"
- " add %3, 1, %3\n"
- "1:\n\t"
- "sllx %3, 32, %3\n\t"
+ "bne,a,pn %%xcc, 1b\n\t"
+ " mov %4, %2\n\t"
+ "sllx %4, 32, %4\n\t"
"or %3, %4, %0\n\t"
: "=&r" (ret), "=&r" (addr),
"=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
return val;
}
-static struct sparc64_tick_ops hbtick_operations = {
+static struct sparc64_tick_ops hbtick_operations __read_mostly = {
.init_tick = hbtick_init_tick,
.get_tick = hbtick_get_tick,
.get_compare = hbtick_get_compare,
* NOTE: On SUN5 systems the ticker interrupt comes in using 2
* interrupts, one at level14 and one with softint bit 0.
*/
-unsigned long timer_tick_offset;
-unsigned long timer_tick_compare;
+unsigned long timer_tick_offset __read_mostly;
-static unsigned long timer_ticks_per_nsec_quotient;
+static unsigned long timer_ticks_per_nsec_quotient __read_mostly;
#define TICK_SIZE (tick_nsec / 1000)
static long last_rtc_update;
/* Determine when to update the Mostek clock. */
- if ((time_status & STA_UNSYNC) == 0 &&
+ if (ntp_synced() &&
xtime.tv_sec > last_rtc_update + 660 &&
(xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
(xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
{
- unsigned long ticks, pstate;
+ unsigned long ticks, compare, pstate;
write_seqlock(&xtime_lock);
do {
#ifndef CONFIG_SMP
profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(regs));
#endif
do_timer(regs);
: "=r" (pstate)
: "i" (PSTATE_IE));
- timer_tick_compare = tick_ops->add_compare(timer_tick_offset);
+ compare = tick_ops->add_compare(timer_tick_offset);
ticks = tick_ops->get_tick();
/* Restore PSTATE_IE. */
__asm__ __volatile__("wrpr %0, 0x0, %%pstate"
: /* no outputs */
: "r" (pstate));
- } while (time_after_eq(ticks, timer_tick_compare));
+ } while (time_after_eq(ticks, compare));
timer_check_rtc();
do_timer(regs);
- /*
- * Only keep timer_tick_offset uptodate, but don't set TICK_CMPR.
- */
- timer_tick_compare = tick_ops->get_compare() + timer_tick_offset;
-
timer_check_rtc();
write_sequnlock(&xtime_lock);
/* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */
static void __init kick_start_clock(void)
{
- unsigned long regs = mstk48t02_regs;
+ void __iomem *regs = mstk48t02_regs;
u8 sec, tmp;
int i, count;
/* Return nonzero if the clock chip battery is low. */
static int __init has_low_battery(void)
{
- unsigned long regs = mstk48t02_regs;
+ void __iomem *regs = mstk48t02_regs;
u8 data1, data2;
spin_lock_irq(&mostek_lock);
static void __init set_system_time(void)
{
unsigned int year, mon, day, hour, min, sec;
- unsigned long mregs = mstk48t02_regs;
+ void __iomem *mregs = mstk48t02_regs;
#ifdef CONFIG_PCI
unsigned long dregs = ds1287_regs;
#else
strcmp(model, "mk48t59") &&
strcmp(model, "m5819") &&
strcmp(model, "m5819p") &&
+ strcmp(model, "m5823") &&
strcmp(model, "ds1287")) {
if (cbus != NULL) {
prom_printf("clock_probe: Central bus lacks timer chip.\n");
if (!strcmp(model, "ds1287") ||
!strcmp(model, "m5819") ||
- !strcmp(model, "m5819p")) {
+ !strcmp(model, "m5819p") ||
+ !strcmp(model, "m5823")) {
ds1287_regs = edev->resource[0].start;
} else {
- mstk48t59_regs = edev->resource[0].start;
+ mstk48t59_regs = (void __iomem *)
+ edev->resource[0].start;
mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
}
break;
}
if (!strcmp(model, "ds1287") ||
!strcmp(model, "m5819") ||
- !strcmp(model, "m5819p")) {
+ !strcmp(model, "m5819p") ||
+ !strcmp(model, "m5823")) {
ds1287_regs = isadev->resource.start;
} else {
- mstk48t59_regs = isadev->resource.start;
+ mstk48t59_regs = (void __iomem *)
+ isadev->resource.start;
mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
}
break;
}
if(model[5] == '0' && model[6] == '2') {
- mstk48t02_regs = (((u64)clk_reg[0].phys_addr) |
- (((u64)clk_reg[0].which_io)<<32UL));
+ mstk48t02_regs = (void __iomem *)
+ (((u64)clk_reg[0].phys_addr) |
+ (((u64)clk_reg[0].which_io)<<32UL));
} else if(model[5] == '0' && model[6] == '8') {
- mstk48t08_regs = (((u64)clk_reg[0].phys_addr) |
- (((u64)clk_reg[0].which_io)<<32UL));
+ mstk48t08_regs = (void __iomem *)
+ (((u64)clk_reg[0].phys_addr) |
+ (((u64)clk_reg[0].which_io)<<32UL));
mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
} else {
- mstk48t59_regs = (((u64)clk_reg[0].phys_addr) |
- (((u64)clk_reg[0].which_io)<<32UL));
+ mstk48t59_regs = (void __iomem *)
+ (((u64)clk_reg[0].phys_addr) |
+ (((u64)clk_reg[0].which_io)<<32UL));
mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
}
break;
}
- if (mstk48t02_regs != 0UL) {
+ if (mstk48t02_regs != NULL) {
/* Report a low battery voltage condition. */
if (has_low_battery())
prom_printf("NVRAM: Low battery voltage!\n");
int err;
/* Register IRQ handler. */
- err = request_irq(build_irq(0, 0, 0UL, 0UL), cfunc, SA_STATIC_ALLOC,
+ err = request_irq(build_irq(0, 0, 0UL, 0UL), cfunc, 0,
"timer", NULL);
if (err) {
};
/* The quotient formula is taken from the IA64 port. */
-#define SPARC64_NSEC_PER_CYC_SHIFT 30UL
+#define SPARC64_NSEC_PER_CYC_SHIFT 10UL
void __init time_init(void)
{
unsigned long clock = sparc64_init_timers();
static int set_rtc_mmss(unsigned long nowtime)
{
int real_seconds, real_minutes, chip_minutes;
- unsigned long mregs = mstk48t02_regs;
+ void __iomem *mregs = mstk48t02_regs;
#ifdef CONFIG_PCI
unsigned long dregs = ds1287_regs;
#else
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