struct amd_page_map {
unsigned long *real;
- unsigned long *remapped;
+ unsigned long __iomem *remapped;
};
static struct _amd_irongate_private {
- volatile u8 *registers;
+ volatile u8 __iomem *registers;
struct amd_page_map **gatt_pages;
int num_tables;
} amd_irongate_private;
}
global_cache_flush();
- for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
- page_map->remapped[i] = agp_bridge->scratch_page;
+ for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
+ writel(agp_bridge->scratch_page, page_map->remapped+i);
+ readl(page_map->remapped+i); /* PCI Posting. */
+ }
return 0;
}
}
agp_bridge->gatt_table_real = (u32 *)page_dir.real;
- agp_bridge->gatt_table = (u32 *)page_dir.remapped;
+ agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
/* Get the address for the gart region.
/* Calculate the agp offset */
for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
- page_dir.remapped[GET_PAGE_DIR_OFF(addr)] =
- virt_to_phys(amd_irongate_private.gatt_pages[i]->real);
- page_dir.remapped[GET_PAGE_DIR_OFF(addr)] |= 0x00000001;
+ writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,
+ page_dir.remapped+GET_PAGE_DIR_OFF(addr));
+ readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */
}
return 0;
struct amd_page_map page_dir;
page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
- page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
+ page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
amd_free_gatt_pages();
amd_free_page_map(&page_dir);
/* Get the memory mapped registers */
pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
- amd_irongate_private.registers = (volatile u8 *) ioremap(temp, 4096);
+ amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
/* Write out the address of the gatt table */
- OUTREG32(amd_irongate_private.registers, AMD_ATTBASE,
- agp_bridge->gatt_bus_addr);
+ writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
+ readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */
/* Write the Sync register */
pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
/* Write the enable register */
- enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
+ enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
enable_reg = (enable_reg | 0x0004);
- OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
+ writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
+ readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
/* Write out the size register */
pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
- temp = (((temp & ~(0x0000000e)) | current_size->size_value)
- | 0x00000001);
+ temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);
pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
/* Flush the tlb */
- OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
-
+ writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
+ readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/
return 0;
}
previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
- enable_reg = INREG16(amd_irongate_private.registers, AMD_GARTENABLE);
+ enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
enable_reg = (enable_reg & ~(0x0004));
- OUTREG16(amd_irongate_private.registers, AMD_GARTENABLE, enable_reg);
+ writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
+ readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
/* Write back the previous size and disable gart translation */
pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
- iounmap((void *) amd_irongate_private.registers);
+ iounmap((void __iomem *) amd_irongate_private.registers);
}
/*
static void amd_irongate_tlbflush(struct agp_memory *temp)
{
- OUTREG32(amd_irongate_private.registers, AMD_TLBFLUSH, 0x00000001);
+ writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
+ readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */
}
static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
{
int i, j, num_entries;
- unsigned long *cur_gatt;
+ unsigned long __iomem *cur_gatt;
unsigned long addr;
num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
while (j < (pg_start + mem->page_count)) {
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
- if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)]))
+ if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
return -EBUSY;
j++;
}
for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
- cur_gatt[GET_GATT_OFF(addr)] =
- agp_generic_mask_memory(mem->memory[i], mem->type);
+ writel(agp_generic_mask_memory(mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
+ readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
}
amd_irongate_tlbflush(mem);
return 0;
static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
{
int i;
- unsigned long *cur_gatt;
+ unsigned long __iomem *cur_gatt;
unsigned long addr;
if (type != 0 || mem->type != 0)
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
cur_gatt = GET_GATT(addr);
- cur_gatt[GET_GATT_OFF(addr)] =
- (unsigned long) agp_bridge->scratch_page;
+ writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
+ readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
}
amd_irongate_tlbflush(mem);
static int __init agp_amdk7_init(void)
{
+ if (agp_off)
+ return -EINVAL;
return pci_module_init(&agp_amdk7_pci_driver);
}