#include <linux/gfp.h>
#include <linux/page-flags.h>
#include <linux/mm.h>
-#include <linux/jiffies.h>
#include "agp.h"
/* NVIDIA registers */
/* Find the iorr that is already used for the base */
/* If not found, determine the uppermost available iorr */
free_iorr_addr = AMD_K7_NUM_IORR;
- for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
+ for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
if ((mask_lo & 0x00000800) == 0)
free_iorr_addr = iorr_addr;
}
-
+
if (iorr_addr >= AMD_K7_NUM_IORR) {
iorr_addr = free_iorr_addr;
if (iorr_addr >= AMD_K7_NUM_IORR)
}
/* attbase */
- for (i = 0; i < 8; i++) {
+ for(i = 0; i < 8; i++) {
pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
(agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
}
static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
{
int i, j;
-
+
if ((type != 0) || (mem->type != 0))
return -EINVAL;
-
+
if ((pg_start + mem->page_count) >
(nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
return -EINVAL;
-
- for (j = pg_start; j < (pg_start + mem->page_count); j++) {
+
+ for(j = pg_start; j < (pg_start + mem->page_count); j++) {
if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j)))
return -EBUSY;
}
do {
pci_read_config_dword(nvidia_private.dev_1,
NVIDIA_1_WBC, &wbc_reg);
- if (time_before_eq(end, jiffies)) {
+ if ((signed)(end - jiffies) <= 0) {
printk(KERN_ERR PFX
"TLB flush took more than 3 seconds.\n");
}
}
/* flush TLB entries */
- for (i = 0; i < 32 + 1; i++)
+ for(i = 0; i < 32 + 1; i++)
temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
- for (i = 0; i < 32 + 1; i++)
+ for(i = 0; i < 32 + 1; i++)
temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
}
pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
nvidia_private.dev_3 =
pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
-
+
if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) {
printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 "
"chipset, but could not find the secondary devices.\n");
agp_put_bridge(bridge);
}
+#ifdef CONFIG_PM
+static int agp_nvidia_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ pci_save_state (pdev);
+ pci_set_power_state (pdev, 3);
+
+ return 0;
+}
+
+static int agp_nvidia_resume(struct pci_dev *pdev)
+{
+ /* set power state 0 and restore PCI space */
+ pci_set_power_state (pdev, 0);
+ pci_restore_state(pdev);
+
+ /* reconfigure AGP hardware again */
+ nvidia_configure();
+
+ return 0;
+}
+#endif
+
+
static struct pci_device_id agp_nvidia_pci_table[] = {
{
.class = (PCI_CLASS_BRIDGE_HOST << 8),
.id_table = agp_nvidia_pci_table,
.probe = agp_nvidia_probe,
.remove = agp_nvidia_remove,
+#ifdef CONFIG_PM
+ .suspend = agp_nvidia_suspend,
+ .resume = agp_nvidia_resume,
+#endif
};
static int __init agp_nvidia_init(void)