*/
static void serverworks_tlbflush(struct agp_memory *temp)
{
- unsigned long end;
-
- OUTREG8(serverworks_private.registers, SVWRKS_POSTFLUSH, 0x01);
- end = jiffies + 3*HZ;
- while(INREG8(serverworks_private.registers,
- SVWRKS_POSTFLUSH) == 0x01) {
- if((signed)(end - jiffies) <= 0) {
- printk(KERN_ERR PFX "Posted write buffer flush took more"
- "then 3 seconds\n");
- }
- }
- OUTREG32(serverworks_private.registers, SVWRKS_DIRFLUSH, 0x00000001);
- end = jiffies + 3*HZ;
- while(INREG32(serverworks_private.registers,
- SVWRKS_DIRFLUSH) == 0x00000001) {
- if((signed)(end - jiffies) <= 0) {
- printk(KERN_ERR PFX "TLB flush took more"
- "then 3 seconds\n");
- }
- }
+ OUTREG8(serverworks_private.registers, SVWRKS_POSTFLUSH, 1);
+ while(INREG8(serverworks_private.registers, SVWRKS_POSTFLUSH) == 1)
+ cpu_relax();
+
+ OUTREG32(serverworks_private.registers, SVWRKS_DIRFLUSH, 1);
+ while(INREG32(serverworks_private.registers, SVWRKS_DIRFLUSH) == 1)
+ cpu_relax();
}
static int serverworks_configure(void)
struct agp_bridge_data *bridge;
struct pci_dev *bridge_dev;
u32 temp, temp2;
+ u8 cap_ptr = 0;
/* Everything is on func 1 here so we are hardcoding function one */
bridge_dev = pci_find_slot((unsigned int)pdev->bus->number,
return -ENODEV;
}
+ cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
+
switch (pdev->device) {
case 0x0006:
/* ServerWorks CNB20HE
break;
default:
- printk(KERN_ERR PFX "Unsupported Serverworks chipset "
- "(device id: %04x)\n", pdev->device);
+ if (cap_ptr)
+ printk(KERN_ERR PFX "Unsupported Serverworks chipset "
+ "(device id: %04x)\n", pdev->device);
return -ENODEV;
}
serverworks_private.svrwrks_dev = bridge_dev;
serverworks_private.gart_addr_ofs = 0x10;
-
+
pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);