*
*/
+#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include "edac_mc.h"
-#define AMD76X_REVISION " Ver: 2.0.1 " __DATE__
-#define EDAC_MOD_STR "amd76x_edac"
-
#define amd76x_printk(level, fmt, arg...) \
edac_printk(level, "amd76x", fmt, ##arg)
static void amd76x_get_error_info(struct mem_ctl_info *mci,
struct amd76x_error_info *info)
{
- struct pci_dev *pdev;
-
- pdev = to_pci_dev(mci->dev);
- pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS,
+ pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS,
&info->ecc_mode_status);
if (info->ecc_mode_status & BIT(8))
- pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
+ pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
(u32) BIT(8), (u32) BIT(8));
if (info->ecc_mode_status & BIT(9))
- pci_write_bits32(pdev, AMD76X_ECC_MODE_STATUS,
+ pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
(u32) BIT(9), (u32) BIT(9));
}
amd76x_process_error_info(mci, &info, 1);
}
-static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
- enum edac_type edac_mode)
-{
- struct csrow_info *csrow;
- u32 mba, mba_base, mba_mask, dms;
- int index;
-
- for (index = 0; index < mci->nr_csrows; index++) {
- csrow = &mci->csrows[index];
-
- /* find the DRAM Chip Select Base address and mask */
- pci_read_config_dword(pdev,
- AMD76X_MEM_BASE_ADDR + (index * 4),
- &mba);
-
- if (!(mba & BIT(0)))
- continue;
-
- mba_base = mba & 0xff800000UL;
- mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
- pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
- csrow->first_page = mba_base >> PAGE_SHIFT;
- csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
- csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
- csrow->page_mask = mba_mask >> PAGE_SHIFT;
- csrow->grain = csrow->nr_pages << PAGE_SHIFT;
- csrow->mtype = MEM_RDDR;
- csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
- csrow->edac_mode = edac_mode;
- }
-}
-
/**
* amd76x_probe1 - Perform set up for detected device
* @pdev; PCI device detected
*/
static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
{
- static const enum edac_type ems_modes[] = {
+ int rc = -ENODEV;
+ int index;
+ struct mem_ctl_info *mci = NULL;
+ enum edac_type ems_modes[] = {
EDAC_NONE,
EDAC_EC,
EDAC_SECDED,
EDAC_SECDED
};
- struct mem_ctl_info *mci = NULL;
u32 ems;
u32 ems_mode;
struct amd76x_error_info discard;
mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);
if (mci == NULL) {
- return -ENOMEM;
+ rc = -ENOMEM;
+ goto fail;
}
debugf0("%s(): mci = %p\n", __func__, mci);
- mci->dev = &pdev->dev;
+ mci->pdev = pdev;
mci->mtype_cap = MEM_FLAG_RDDR;
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
mci->edac_cap = ems_mode ?
(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
mci->mod_name = EDAC_MOD_STR;
- mci->mod_ver = AMD76X_REVISION;
+ mci->mod_ver = "$Revision: 1.4.2.5 $";
mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
mci->edac_check = amd76x_check;
mci->ctl_page_to_phys = NULL;
- amd76x_init_csrows(mci, pdev, ems_modes[ems_mode]);
+ for (index = 0; index < mci->nr_csrows; index++) {
+ struct csrow_info *csrow = &mci->csrows[index];
+ u32 mba;
+ u32 mba_base;
+ u32 mba_mask;
+ u32 dms;
+
+ /* find the DRAM Chip Select Base address and mask */
+ pci_read_config_dword(mci->pdev,
+ AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
+
+ if (!(mba & BIT(0)))
+ continue;
+
+ mba_base = mba & 0xff800000UL;
+ mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
+ pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS,
+ &dms);
+ csrow->first_page = mba_base >> PAGE_SHIFT;
+ csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
+ csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
+ csrow->page_mask = mba_mask >> PAGE_SHIFT;
+ csrow->grain = csrow->nr_pages << PAGE_SHIFT;
+ csrow->mtype = MEM_RDDR;
+ csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
+ csrow->edac_mode = ems_modes[ems_mode];
+ }
+
amd76x_get_error_info(mci, &discard); /* clear counters */
- /* Here we assume that we will never see multiple instances of this
- * type of memory controller. The ID is therefore hardcoded to 0.
- */
- if (edac_mc_add_mc(mci,0)) {
+ if (edac_mc_add_mc(mci)) {
debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
goto fail;
}
return 0;
fail:
- edac_mc_free(mci);
- return -ENODEV;
+ if (mci != NULL)
+ edac_mc_free(mci);
+ return rc;
}
/* returns count (>= 0), or negative on error */
debugf0("%s()\n", __func__);
- if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
+ if ((mci = edac_mc_del_mc(pdev)) == NULL)
return;
edac_mc_free(mci);