-
/*
- * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
+ * linux/drivers/ide/pci/it8212.c Version 0.07 November 2004
*
* Copyright (C) 2004 Red Hat <alan@redhat.com>
*
* modes. In pass through mode then it is an IDE controller. In its smart
* mode its actually quite a capable hardware raid controller disguised
* as an IDE controller. Smart mode only understands DMA read/write and
- * identify, none of the fancier commands apply. The IT8211 is identical
- * in other respects but lacks the raid mode.
+ * identify, none of the fancier commands apply.
*
* Errata:
* o Rev 0x10 also requires master/slave hold the same DMA timings and
* TODO
* - ATAPI UDMA is ok but not MWDMA it seems
* - RAID configuration ioctls
- * - Move to libata once it grows up
*/
#include <linux/config.h>
#include <asm/io.h>
-struct it821x_dev
+struct it8212_dev
{
unsigned int smart:1, /* Are we in smart raid mode */
timing10:1; /* Rev 0x10 */
static int it8212_noraid;
/**
- * it821x_program - program the PIO/MWDMA registers
+ * it8212_program - program the PIO/MWDMA registers
* @drive: drive to tune
*
* Program the PIO/MWDMA timing for this channel according to the
* current clock.
*/
-static void it821x_program(ide_drive_t *drive, u16 timing)
+static void it8212_program(ide_drive_t *drive, u16 timing)
{
- ide_hwif_t *hwif = drive->hwif;
- struct it821x_dev *itdev = ide_get_hwifdata(hwif);
+ ide_hwif_t *hwif = HWIF(drive);
+ struct it8212_dev *itdev = ide_get_hwifdata(hwif);
int channel = hwif->channel;
u8 conf;
}
/**
- * it821x_program_udma - program the UDMA registers
+ * it8212_program_udma - program the UDMA registers
* @drive: drive to tune
*
* Program the UDMA timing for this drive according to the
* current clock.
*/
-static void it821x_program_udma(ide_drive_t *drive, u16 timing)
+static void it8212_program_udma(ide_drive_t *drive, u16 timing)
{
- ide_hwif_t *hwif = drive->hwif;
- struct it821x_dev *itdev = ide_get_hwifdata(hwif);
+ ide_hwif_t *hwif = HWIF(drive);
+ struct it8212_dev *itdev = ide_get_hwifdata(hwif);
int channel = hwif->channel;
int unit = drive->select.b.unit;
u8 conf;
/**
- * it821x_clock_strategy
+ * it8212_clock_strategy
* @hwif: hardware interface
*
* Select between the 50 and 66Mhz base clocks to get the best
* results for this interface.
*/
-static void it821x_clock_strategy(ide_drive_t *drive)
+static void it8212_clock_strategy(ide_drive_t *drive)
{
- ide_hwif_t *hwif = drive->hwif;
- struct it821x_dev *itdev = ide_get_hwifdata(hwif);
+ ide_hwif_t *hwif = HWIF(drive);
+ struct it8212_dev *itdev = ide_get_hwifdata(hwif);
u8 unit = drive->select.b.unit;
ide_drive_t *pair = &hwif->drives[1-unit];
* MWDMA will be dealt with by the dma switcher
*/
if(pair && itdev->udma[1-unit] != UDMA_OFF) {
- it821x_program_udma(pair, itdev->udma[1-unit]);
- it821x_program(pair, itdev->pio[1-unit]);
+ it8212_program_udma(pair, itdev->udma[1-unit]);
+ it8212_program(pair, itdev->pio[1-unit]);
}
/*
* Reprogram the UDMA/PIO of our drive for the switch.
* MWDMA will be dealt with by the dma switcher
*/
if(itdev->udma[unit] != UDMA_OFF) {
- it821x_program_udma(drive, itdev->udma[unit]);
- it821x_program(drive, itdev->pio[unit]);
+ it8212_program_udma(drive, itdev->udma[unit]);
+ it8212_program(drive, itdev->pio[unit]);
}
}
/**
- * it821x_ratemask - Compute available modes
+ * it8212_ratemask - Compute available modes
* @drive: IDE drive
*
* Compute the available speeds for the devices on the interface. This
* is all modes to ATA133 clipped by drive cable setup.
*/
-static u8 it821x_ratemask (ide_drive_t *drive)
+static byte it8212_ratemask (ide_drive_t *drive)
{
u8 mode = 4;
if (!eighty_ninty_three(drive))
}
/**
- * it821x_tuneproc - tune a drive
+ * it8212_tuneproc - tune a drive
* @drive: drive to tune
* @mode_wanted: the target operating mode
*
* This code is only used in pass through mode.
*/
-static void it821x_tuneproc (ide_drive_t *drive, byte mode_wanted)
+static void it8212_tuneproc (ide_drive_t *drive, byte mode_wanted)
{
- ide_hwif_t *hwif = drive->hwif;
- struct it821x_dev *itdev = ide_get_hwifdata(hwif);
+ ide_hwif_t *hwif = HWIF(drive);
+ struct it8212_dev *itdev = ide_get_hwifdata(hwif);
int unit = drive->select.b.unit;
/* Spec says 89 ref driver uses 88 */
itdev->want[unit][1] = pio_want[mode_wanted];
itdev->want[unit][0] = 1; /* PIO is lowest priority */
itdev->pio[unit] = pio[mode_wanted];
- it821x_clock_strategy(drive);
- it821x_program(drive, itdev->pio[unit]);
+ it8212_clock_strategy(drive);
+ it8212_program(drive, itdev->pio[unit]);
}
/**
- * it821x_tune_mwdma - tune a channel for MWDMA
+ * it8212_tune_mwdma - tune a channel for MWDMA
* @drive: drive to set up
* @mode_wanted: the target operating mode
*
* the shared MWDMA/PIO timing register.
*/
-static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
+static void it8212_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
{
- ide_hwif_t *hwif = drive->hwif;
- struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
+ ide_hwif_t *hwif = HWIF(drive);
+ struct it8212_dev *itdev = (void *)ide_get_hwifdata(hwif);
int unit = drive->select.b.unit;
int channel = hwif->channel;
u8 conf;
conf |= 1 << (3 + 2 * channel + unit);
pci_write_config_byte(hwif->pci_dev, 0x50, conf);
- it821x_clock_strategy(drive);
+ it8212_clock_strategy(drive);
/* FIXME: do we need to program this ? */
- /* it821x_program(drive, itdev->mwdma[unit]); */
+ /* it8212_program(drive, itdev->mwdma[unit]); */
}
/**
- * it821x_tune_udma - tune a channel for UDMA
+ * it8212_tune_udma - tune a channel for UDMA
* @drive: drive to set up
* @mode_wanted: the target operating mode
*
* controller when doing UDMA modes in pass through.
*/
-static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
+static void it8212_tune_udma (ide_drive_t *drive, byte mode_wanted)
{
- ide_hwif_t *hwif = drive->hwif;
- struct it821x_dev *itdev = ide_get_hwifdata(hwif);
+ ide_hwif_t *hwif = HWIF(drive);
+ struct it8212_dev *itdev = ide_get_hwifdata(hwif);
int unit = drive->select.b.unit;
int channel = hwif->channel;
u8 conf;
conf &= ~ (1 << (3 + 2 * channel + unit));
pci_write_config_byte(hwif->pci_dev, 0x50, conf);
- it821x_clock_strategy(drive);
- it821x_program_udma(drive, itdev->udma[unit]);
+ it8212_clock_strategy(drive);
+ it8212_program_udma(drive, itdev->udma[unit]);
}
/**
- * config_it821x_chipset_for_pio - set drive timings
+ * config_it8212_chipset_for_pio - set drive timings
* @drive: drive to tune
* @speed we want
*
* on the cable.
*/
-static void config_it821x_chipset_for_pio (ide_drive_t *drive, byte set_speed)
+static void config_it8212_chipset_for_pio (ide_drive_t *drive, byte set_speed)
{
u8 unit = drive->select.b.unit;
- ide_hwif_t *hwif = drive->hwif;
+ ide_hwif_t *hwif = HWIF(drive);
ide_drive_t *pair = &hwif->drives[1-unit];
- u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
+ u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
u8 pair_pio;
/* We have to deal with this mess in pairs */
if(pair != NULL) {
- pair_pio = ide_get_best_pio_mode(pair, 255, 5, NULL);
+ pair_pio = ide_get_best_pio_mode(pair, 4, 5, NULL);
/* Trim PIO to the slowest of the master/slave */
if(pair_pio < set_pio)
set_pio = pair_pio;
}
- it821x_tuneproc(drive, set_pio);
+ it8212_tuneproc(drive, set_pio);
speed = XFER_PIO_0 + set_pio;
/* XXX - We trim to the lowest of the pair so the other drive
will always be fine at this point until we do hotplug passthru */
(void) ide_config_drive_speed(drive, speed);
}
+static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
+{
+ config_it8212_chipset_for_pio(drive, set_speed);
+}
+
/**
- * it821x_dma_read - DMA hook
+ * it8212_dma_read - DMA hook
* @drive: drive for DMA
*
- * The IT821x has a single timing register for MWDMA and for PIO
+ * The IT8212 has a single timing register for MWDMA and for PIO
* operations. As we flip back and forth we have to reload the
* clock. In addition the rev 0x10 device only works if the same
* timing value is loaded into the master and slave UDMA clock
* FIXME: we could figure out in advance if we need to do reloads
*/
-static void it821x_dma_start(ide_drive_t *drive)
+static int it8212_dma_begin(ide_drive_t *drive)
{
- ide_hwif_t *hwif = drive->hwif;
- struct it821x_dev *itdev = ide_get_hwifdata(hwif);
+ ide_hwif_t *hwif = HWIF(drive);
+ struct it8212_dev *itdev = ide_get_hwifdata(hwif);
int unit = drive->select.b.unit;
if(itdev->mwdma[unit] != MWDMA_OFF)
- it821x_program(drive, itdev->mwdma[unit]);
+ it8212_program(drive, itdev->mwdma[unit]);
else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
- it821x_program_udma(drive, itdev->udma[unit]);
- ide_dma_start(drive);
+ it8212_program_udma(drive, itdev->udma[unit]);
+ return __ide_dma_begin(drive);
}
/**
- * it821x_dma_write - DMA hook
+ * it8212_dma_write - DMA hook
* @drive: drive for DMA stop
*
- * The IT821x has a single timing register for MWDMA and for PIO
+ * The IT8212 has a single timing register for MWDMA and for PIO
* operations. As we flip back and forth we have to reload the
* clock.
*/
-static int it821x_dma_end(ide_drive_t *drive)
+static int it8212_dma_end(ide_drive_t *drive)
{
- ide_hwif_t *hwif = drive->hwif;
+ ide_hwif_t *hwif = HWIF(drive);
int unit = drive->select.b.unit;
- struct it821x_dev *itdev = ide_get_hwifdata(hwif);
+ struct it8212_dev *itdev = ide_get_hwifdata(hwif);
int ret = __ide_dma_end(drive);
if(itdev->mwdma[unit] != MWDMA_OFF)
- it821x_program(drive, itdev->pio[unit]);
+ it8212_program(drive, itdev->pio[unit]);
return ret;
}
/**
- * it821x_tune_chipset - set controller timings
+ * it8212_tune_chipset - set controller timings
* @drive: Drive to set up
* @xferspeed: speed we want to achieve
*
* make the thing work.
*/
-static int it821x_tune_chipset (ide_drive_t *drive, byte xferspeed)
+static int it8212_tune_chipset (ide_drive_t *drive, byte xferspeed)
{
- ide_hwif_t *hwif = drive->hwif;
- struct it821x_dev *itdev = ide_get_hwifdata(hwif);
- u8 speed = ide_rate_filter(it821x_ratemask(drive), xferspeed);
-
- if(!itdev->smart) {
- switch(speed) {
- case XFER_PIO_4:
- case XFER_PIO_3:
- case XFER_PIO_2:
- case XFER_PIO_1:
- case XFER_PIO_0:
- it821x_tuneproc(drive, (speed - XFER_PIO_0));
- break;
- /* MWDMA tuning is really hard because our MWDMA and PIO
- timings are kept in the same place. We can switch in the
- host dma on/off callbacks */
- case XFER_MW_DMA_2:
- case XFER_MW_DMA_1:
- case XFER_MW_DMA_0:
- it821x_tune_mwdma(drive, (speed - XFER_MW_DMA_0));
- break;
- case XFER_UDMA_6:
- case XFER_UDMA_5:
- case XFER_UDMA_4:
- case XFER_UDMA_3:
- case XFER_UDMA_2:
- case XFER_UDMA_1:
- case XFER_UDMA_0:
- it821x_tune_udma(drive, (speed - XFER_UDMA_0));
- break;
- default:
- return 1;
- }
+ ide_hwif_t *hwif = HWIF(drive);
+ struct it8212_dev *itdev = ide_get_hwifdata(hwif);
+ u8 speed = ide_rate_filter(it8212_ratemask(drive), xferspeed);
+
+ switch(speed) {
+ case XFER_PIO_4:
+ case XFER_PIO_3:
+ case XFER_PIO_2:
+ case XFER_PIO_1:
+ case XFER_PIO_0:
+ it8212_tuneproc(drive, (speed - XFER_PIO_0));
+ break;
+ /* MWDMA tuning is really hard because our MWDMA and PIO
+ timings are kept in the same place. We can switch in the
+ host dma on/off callbacks */
+ case XFER_MW_DMA_2:
+ case XFER_MW_DMA_1:
+ case XFER_MW_DMA_0:
+ if(!itdev->smart)
+ it8212_tune_mwdma(drive, (speed - XFER_MW_DMA_0));
+ break;
+ case XFER_UDMA_6:
+ case XFER_UDMA_5:
+ case XFER_UDMA_4:
+ case XFER_UDMA_3:
+ case XFER_UDMA_2:
+ case XFER_UDMA_1:
+ case XFER_UDMA_0:
+ if(!itdev->smart)
+ it8212_tune_udma(drive, (speed - XFER_UDMA_0));
+ break;
+ default:
+ return 1;
}
/*
* In smart mode the clocking is done by the host controller
* snooping the mode we picked. The rest of it is not our problem
*/
- return ide_config_drive_speed(drive, speed);
+ return (ide_config_drive_speed(drive, speed));
}
/**
static int config_chipset_for_dma (ide_drive_t *drive)
{
- u8 speed = ide_dma_speed(drive, it821x_ratemask(drive));
+ u8 speed = ide_dma_speed(drive, it8212_ratemask(drive));
+
+ config_chipset_for_pio(drive, !speed);
+
+ if (!speed)
+ return 0;
+
+ if (ide_set_xfer_rate(drive, speed))
+ return 0;
+
+ if (!drive->init_speed)
+ drive->init_speed = speed;
- config_it821x_chipset_for_pio(drive, !speed);
- it821x_tune_chipset(drive, speed);
return ide_dma_enable(drive);
}
/**
- * it821x_configure_drive_for_dma - set up for DMA transfers
+ * it8212_configure_drive_for_dma - set up for DMA transfers
* @drive: drive we are going to set up
*
* Set up the drive for DMA, tune the controller and drive as
* PIO appropriately
*/
-static int it821x_config_drive_for_dma (ide_drive_t *drive)
+static int it8212_config_drive_for_dma (ide_drive_t *drive)
{
- ide_hwif_t *hwif = drive->hwif;
-
- if (ide_use_dma(drive)) {
- if (config_chipset_for_dma(drive))
- return hwif->ide_dma_on(drive);
+ ide_hwif_t *hwif = HWIF(drive);
+ struct hd_driveid *id = drive->id;
+
+ if ((id->capability & 1) != 0 && drive->autodma) {
+ /* Consult the list of known "bad" drives */
+ if (__ide_dma_bad_drive(drive))
+ goto fast_ata_pio;
+
+ if ((id->field_valid & 4) && it8212_ratemask(drive)) {
+ if (id->dma_ultra & hwif->ultra_mask) {
+ /* Force if Capable UltraDMA */
+ int dma = config_chipset_for_dma(drive);
+ if ((id->field_valid & 2) && !dma)
+ goto try_dma_modes;
+ }
+ } else if (id->field_valid & 2) {
+try_dma_modes:
+ if ((id->dma_mword & hwif->mwdma_mask) ||
+ (id->dma_1word & hwif->swdma_mask)) {
+ /* Force if Capable regular DMA modes */
+ if (!config_chipset_for_dma(drive))
+ goto no_dma_set;
+ }
+ } else if (__ide_dma_good_drive(drive) &&
+ (id->eide_dma_time < 150)) {
+ /* Consult the list of known "good" drives */
+ if (!config_chipset_for_dma(drive))
+ goto no_dma_set;
+ } else {
+ goto fast_ata_pio;
+ }
+ return hwif->ide_dma_on(drive);
+ } else if ((id->capability & 8) || (id->field_valid & 2)) {
+fast_ata_pio:
+no_dma_set:
+ config_chipset_for_pio(drive, 1);
+ return hwif->ide_dma_off_quietly(drive);
}
- config_it821x_chipset_for_pio(drive, 1);
- return hwif->ide_dma_off_quietly(drive);
+ /* IORDY not supported */
+ return 0;
}
/**
- * ata66_it821x - check for 80 pin cable
+ * init_chipset_it8212 - set up an ITE device
+ * @dev: PCI device
+ * @name: device name
+ *
+ * PCI chipset level initialize. Nothing to do.
+ */
+
+static unsigned int __devinit init_chipset_it8212(struct pci_dev *dev, const char *name)
+{
+ return 0;
+}
+
+/**
+ * ata66_it8212 - check for 80 pin cable
* @hwif: interface to check
*
* Check for the presence of an ATA66 capable cable on the
* the needed logic onboard.
*/
-static unsigned int __devinit ata66_it821x(ide_hwif_t *hwif)
+static unsigned int __devinit ata66_it8212(ide_hwif_t *hwif)
{
/* The reference driver also only does disk side */
return 1;
}
/**
- * it821x_fixup - post init callback
+ * it8212_fixup - post init callback
* @hwif: interface
*
* This callback is run after the drives have been probed but
* final tuning that is needed, or fixups to work around bugs.
*/
-static void __devinit it821x_fixups(ide_hwif_t *hwif)
+static void __devinit it8212_fixups(ide_hwif_t *hwif)
{
- struct it821x_dev *itdev = ide_get_hwifdata(hwif);
+ struct it8212_dev *itdev = ide_get_hwifdata(hwif);
int i;
if(!itdev->smart) {
/*
* If we are in pass through mode then not much
* needs to be done, but we do bother to clear the
- * IRQ mask as we may well be in PIO (eg rev 0x10)
- * for now and we know unmasking is safe on this chipset.
+ * IRQ mask in case the drives are PIO (eg rev 0x10)
+ * for now.
*/
for (i = 0; i < 2; i++) {
ide_drive_t *drive = &hwif->drives[i];
/* Check for RAID v native */
if(strstr(id->model, "Integrated Technology Express")) {
- /* In raid mode the ident block is slightly buggy
- We need to set the bits so that the IDE layer knows
- LBA28. LBA48 and DMA ar valid */
+ /* In raid mode the ident block is slightly buggy */
id->capability |= 3; /* LBA28, DMA */
id->command_set_2 |= 0x0400; /* LBA48 valid */
id->cfs_enable_2 |= 0x0400; /* LBA48 on */
if(idbits[129] != 1)
printk("(%dK stripe)", idbits[146]);
printk(".\n");
- /* Now the core code will have wrongly decided no DMA
- so we need to fix this */
- hwif->ide_dma_off_quietly(drive);
-#ifdef CONFIG_IDEDMA_ONLYDISK
- if (drive->media == ide_disk)
-#endif
- hwif->ide_dma_check(drive);
} else {
/* Non RAID volume. Fixups to stop the core code
doing unsupported things */
}
/**
- * init_hwif_it821x - set up hwif structs
+ * init_hwif_it8212 - set up hwif structs
* @hwif: interface to set up
*
* We do the basic set up of the interface structure. The IT8212
* ide DMA handlers appropriately
*/
-static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
+static void __devinit init_hwif_it8212(ide_hwif_t *hwif)
{
- struct it821x_dev *idev = kmalloc(sizeof(struct it821x_dev), GFP_KERNEL);
+ struct it8212_dev *idev = kmalloc(sizeof(struct it8212_dev), GFP_KERNEL);
u8 conf;
+ static char *mode[2] = { "pass through", "smart" };
if(idev == NULL) {
- printk(KERN_ERR "it821x: out of memory, falling back to legacy behaviour.\n");
+ printk(KERN_ERR "it8212: out of memory, falling back to legacy behaviour.\n");
goto fallback;
}
- memset(idev, 0, sizeof(struct it821x_dev));
+ memset(idev, 0, sizeof(struct it8212_dev));
ide_set_hwifdata(hwif, idev);
+ /* Force the card into bypass mode if so requested */
+ if (it8212_noraid) {
+ printk(KERN_INFO "it8212: forcing bypass mode.\n");
+
+ /* Reset local CPU, and set BIOS not ready */
+ pci_write_config_byte(hwif->pci_dev, 0x5E, 0x01);
+
+ /* Set to bypass mode, and reset PCI bus */
+ pci_write_config_byte(hwif->pci_dev, 0x50, 0x00);
+
+ pci_write_config_word(hwif->pci_dev, PCI_COMMAND,
+ PCI_COMMAND_PARITY | PCI_COMMAND_IO |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ pci_write_config_word(hwif->pci_dev, 0x40, 0xA0F3);
+
+ pci_write_config_dword(hwif->pci_dev,0x4C, 0x02040204);
+ pci_write_config_byte(hwif->pci_dev, 0x42, 0x36);
+ pci_write_config_byte(hwif->pci_dev, PCI_LATENCY_TIMER, 0);
+ }
+
pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
if(conf & 1) {
idev->smart = 1;
hwif->rqsize = 256;
}
- /* Pull the current clocks from 0x50 also */
+ if(hwif->channel == 0)
+ printk(KERN_INFO "it8212: controller in %s mode.\n",
+ mode[idev->smart]);
+
+ pci_read_config_byte(hwif->pci_dev, 0x50, &conf);
if (conf & (1 << (1 + hwif->channel)))
idev->clock_mode = ATA_50;
else
idev->timing10 = 1;
hwif->atapi_dma = 0;
if(!idev->smart)
- printk(KERN_WARNING "it821x: Revision 0x10, workarounds activated.\n");
+ printk(KERN_WARNING "it8212: Revision 0x10, workarounds activated.\n");
}
- hwif->speedproc = &it821x_tune_chipset;
- hwif->tuneproc = &it821x_tuneproc;
+ hwif->speedproc = &it8212_tune_chipset;
+ hwif->tuneproc = &it8212_tuneproc;
/* MWDMA/PIO clock switching for pass through mode */
if(!idev->smart) {
- hwif->ide_dma_start = &it821x_dma_start;
- hwif->ide_dma_end = &it821x_dma_end;
+ hwif->ide_dma_begin = &it8212_dma_begin;
+ hwif->ide_dma_end = &it8212_dma_end;
}
- hwif->drives[0].autotune = 1;
- hwif->drives[1].autotune = 1;
-
if (!hwif->dma_base)
goto fallback;
hwif->mwdma_mask = 0x07;
hwif->swdma_mask = 0x07;
- hwif->ide_dma_check = &it821x_config_drive_for_dma;
+ hwif->ide_dma_check = &it8212_config_drive_for_dma;
if (!(hwif->udma_four))
- hwif->udma_four = ata66_it821x(hwif);
+ hwif->udma_four = ata66_it8212(hwif);
/*
* The BIOS often doesn't set up DMA on this controller
hwif->drives[0].autodma = hwif->autodma;
hwif->drives[1].autodma = hwif->autodma;
return;
+
fallback:
hwif->autodma = 0;
+ hwif->drives[0].autotune = 1;
+ hwif->drives[1].autotune = 1;
return;
}
-static void __devinit it8212_disable_raid(struct pci_dev *dev)
-{
- /* Reset local CPU, and set BIOS not ready */
- pci_write_config_byte(dev, 0x5E, 0x01);
-
- /* Set to bypass mode, and reset PCI bus */
- pci_write_config_byte(dev, 0x50, 0x00);
- pci_write_config_word(dev, PCI_COMMAND,
- PCI_COMMAND_PARITY | PCI_COMMAND_IO |
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- pci_write_config_word(dev, 0x40, 0xA0F3);
-
- pci_write_config_dword(dev,0x4C, 0x02040204);
- pci_write_config_byte(dev, 0x42, 0x36);
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0);
-}
-
-static unsigned int __devinit init_chipset_it821x(struct pci_dev *dev, const char *name)
-{
- u8 conf;
- static char *mode[2] = { "pass through", "smart" };
-
- /* Force the card into bypass mode if so requested */
- if (it8212_noraid) {
- printk(KERN_INFO "it8212: forcing bypass mode.\n");
- it8212_disable_raid(dev);
- }
- pci_read_config_byte(dev, 0x50, &conf);
- printk(KERN_INFO "it821x: controller in %s mode.\n", mode[conf & 1]);
- return 0;
-}
-
-
#define DECLARE_ITE_DEV(name_str) \
{ \
.name = name_str, \
- .init_chipset = init_chipset_it821x, \
- .init_hwif = init_hwif_it821x, \
+ .init_chipset = init_chipset_it8212, \
+ .init_hwif = init_hwif_it8212, \
.channels = 2, \
.autodma = AUTODMA, \
.bootable = ON_BOARD, \
- .fixup = it821x_fixups \
+ .fixup = it8212_fixups \
}
-static ide_pci_device_t it821x_chipsets[] __devinitdata = {
+static ide_pci_device_t it8212_chipsets[] __devinitdata = {
/* 0 */ DECLARE_ITE_DEV("IT8212"),
};
/**
- * it821x_init_one - pci layer discovery entry
+ * it8212_init_one - pci layer discovery entry
* @dev: PCI device
* @id: ident table entry
*
- * Called by the PCI code when it finds an ITE821x controller.
+ * Called by the PCI code when it finds an ITE8212 controller.
* We then use the IDE PCI generic helper to do most of the work.
*/
-static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
+static int __devinit it8212_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
- ide_setup_pci_device(dev, &it821x_chipsets[id->driver_data]);
+ ide_setup_pci_device(dev, &it8212_chipsets[id->driver_data]);
return 0;
}
-static struct pci_device_id it821x_pci_tbl[] = {
- { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+static struct pci_device_id it8212_pci_tbl[] = {
{ PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8212, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{ 0, },
};
-MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
+MODULE_DEVICE_TABLE(pci, it8212_pci_tbl);
static struct pci_driver driver = {
- .name = "ITE821x IDE",
- .id_table = it821x_pci_tbl,
- .probe = it821x_init_one,
+ .name = "ITE8212 IDE",
+ .id_table = it8212_pci_tbl,
+ .probe = it8212_init_one,
};
-static int __init it821x_ide_init(void)
+static int __init it8212_ide_init(void)
{
return ide_pci_register_driver(&driver);
}
-module_init(it821x_ide_init);
+module_init(it8212_ide_init);
module_param_named(noraid, it8212_noraid, int, S_IRUGO);
MODULE_PARM_DESC(it8212_noraid, "Force card into bypass mode");
MODULE_AUTHOR("Alan Cox");
-MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
+MODULE_DESCRIPTION("PCI driver module for the ITE 8212");
MODULE_LICENSE("GPL");
git://git.onelab.eu / linux-2.6.git / blobdiff