*
*/
+#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/slab.h>
/* Module Parameters */
static int phys_dma = 1;
-module_param(phys_dma, int, 0444);
+module_param(phys_dma, int, 0644);
MODULE_PARM_DESC(phys_dma, "Enable physical dma (default = 1).");
static void dma_trm_tasklet(unsigned long data);
/* Initialize IR Legacy DMA channel mask */
ohci->ir_legacy_channels = 0;
- /* Accept AR requests from all nodes */
- reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
-
- /* Set the address range of the physical response unit.
- * Most controllers do not implement it as a writable register though.
- * They will keep a hardwired offset of 0x00010000 and show 0x0 as
- * register content.
- * To actually enable physical responses is the job of our interrupt
- * handler which programs the physical request filter. */
- reg_write(ohci, OHCI1394_PhyUpperBound,
- OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED >> 16);
-
- DBGMSG("physUpperBoundOffset=%08x",
- reg_read(ohci, OHCI1394_PhyUpperBound));
+ /*
+ * Accept AT requests from all nodes. This probably
+ * will have to be controlled from the subsystem
+ * on a per node basis.
+ */
+ reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000);
/* Specify AT retries */
reg_write(ohci, OHCI1394_ATRetries,
OHCI1394_reqTxComplete |
OHCI1394_isochRx |
OHCI1394_isochTx |
- OHCI1394_postedWriteErr |
- OHCI1394_cycleTooLong |
OHCI1394_cycleInconsistent);
/* Enable link */
reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
buf = reg_read(ohci, OHCI1394_Version);
+#ifndef __sparc__
sprintf (irq_buf, "%d", ohci->dev->irq);
+#else
+ sprintf (irq_buf, "%s", __irq_itoa(ohci->dev->irq));
+#endif
PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%s] "
- "MMIO=[%llx-%llx] Max Packet=[%d] IR/IT contexts=[%d/%d]",
+ "MMIO=[%lx-%lx] Max Packet=[%d] IR/IT contexts=[%d/%d]",
((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),
((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), irq_buf,
- (unsigned long long)pci_resource_start(ohci->dev, 0),
- (unsigned long long)pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,
+ pci_resource_start(ohci->dev, 0),
+ pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,
ohci->max_packet_size,
ohci->nb_iso_rcv_ctx, ohci->nb_iso_xmit_ctx);
event &= ~OHCI1394_unrecoverableError;
}
- if (event & OHCI1394_postedWriteErr) {
- PRINT(KERN_ERR, "physical posted write error");
- /* no recovery strategy yet, had to involve protocol drivers */
- }
- if (event & OHCI1394_cycleTooLong) {
- if(printk_ratelimit())
- PRINT(KERN_WARNING, "isochronous cycle too long");
- else
- DBGMSG("OHCI1394_cycleTooLong");
- reg_write(ohci, OHCI1394_LinkControlSet,
- OHCI1394_LinkControl_CycleMaster);
- event &= ~OHCI1394_cycleTooLong;
- }
+
if (event & OHCI1394_cycleInconsistent) {
/* We subscribe to the cycleInconsistent event only to
* clear the corresponding event bit... otherwise,
DBGMSG("OHCI1394_cycleInconsistent");
event &= ~OHCI1394_cycleInconsistent;
}
+
if (event & OHCI1394_busReset) {
/* The busReset event bit can't be cleared during the
* selfID phase, so we disable busReset interrupts, to
}
event &= ~OHCI1394_busReset;
}
+
if (event & OHCI1394_reqTxComplete) {
struct dma_trm_ctx *d = &ohci->at_req_context;
DBGMSG("Got reqTxComplete interrupt "
reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
spin_unlock_irqrestore(&ohci->event_lock, flags);
+ /* Accept Physical requests from all nodes. */
+ reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0xffffffff);
+ reg_write(ohci,OHCI1394_AsReqFilterLoSet, 0xffffffff);
+
/* Turn on phys dma reception.
*
* TODO: Enable some sort of filtering management.
*/
if (phys_dma) {
- reg_write(ohci, OHCI1394_PhyReqFilterHiSet,
- 0xffffffff);
- reg_write(ohci, OHCI1394_PhyReqFilterLoSet,
- 0xffffffff);
+ reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0xffffffff);
+ reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0xffffffff);
+ reg_write(ohci,OHCI1394_PhyUpperBound, 0x01000000);
+ } else {
+ reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0x00000000);
+ reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0x00000000);
}
DBGMSG("PhyReqFilter=%08x%08x",
- reg_read(ohci, OHCI1394_PhyReqFilterHiSet),
- reg_read(ohci, OHCI1394_PhyReqFilterLoSet));
+ reg_read(ohci,OHCI1394_PhyReqFilterHiSet),
+ reg_read(ohci,OHCI1394_PhyReqFilterLoSet));
hpsb_selfid_complete(host, phyid, isroot);
} else
{
struct hpsb_host *host;
struct ti_ohci *ohci; /* shortcut to currently handled device */
- resource_size_t ohci_base;
+ unsigned long ohci_base;
if (pci_enable_device(dev))
FAIL(-ENXIO, "Failed to enable OHCI hardware");
* fail to report the right length. Anyway, the ohci spec
* clearly says it's 2kb, so this shouldn't be a problem. */
ohci_base = pci_resource_start(dev, 0);
- if (pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE)
- PRINT(KERN_WARNING, "PCI resource length of 0x%llx too small!",
- (unsigned long long)pci_resource_len(dev, 0));
+ if (pci_resource_len(dev, 0) != OHCI1394_REGISTER_SIZE)
+ PRINT(KERN_WARNING, "Unexpected PCI resource length of %lx!",
+ pci_resource_len(dev, 0));
/* Seems PCMCIA handles this internally. Not sure why. Seems
* pretty bogus to force a driver to special case this. */
#ifndef PCMCIA
if (!request_mem_region (ohci_base, OHCI1394_REGISTER_SIZE, OHCI1394_DRIVER_NAME))
- FAIL(-ENOMEM, "MMIO resource (0x%llx - 0x%llx) unavailable",
- (unsigned long long)ohci_base,
- (unsigned long long)ohci_base + OHCI1394_REGISTER_SIZE);
+ FAIL(-ENOMEM, "MMIO resource (0x%lx - 0x%lx) unavailable",
+ ohci_base, ohci_base + OHCI1394_REGISTER_SIZE);
#endif
ohci->init_state = OHCI_INIT_HAVE_MEM_REGION;
spin_lock_init(&ohci->event_lock);
/*
- * interrupts are disabled, all right, but... due to IRQF_SHARED we
+ * interrupts are disabled, all right, but... due to SA_SHIRQ we
* might get called anyway. We'll see no event, of course, but
* we need to get to that "no event", so enough should be initialized
* by that point.
*/
- if (request_irq(dev->irq, ohci_irq_handler, IRQF_SHARED,
+ if (request_irq(dev->irq, ohci_irq_handler, SA_SHIRQ,
OHCI1394_DRIVER_NAME, ohci))
FAIL(-ENOMEM, "Failed to allocate shared interrupt %d", dev->irq);
host->csr.max_rec = (reg_read(ohci, OHCI1394_BusOptions) >> 12) & 0xf;
host->csr.lnk_spd = reg_read(ohci, OHCI1394_BusOptions) & 0x7;
- if (phys_dma) {
- host->low_addr_space =
- (u64) reg_read(ohci, OHCI1394_PhyUpperBound) << 16;
- if (!host->low_addr_space)
- host->low_addr_space = OHCI1394_PHYS_UPPER_BOUND_FIXED;
- }
- host->middle_addr_space = OHCI1394_MIDDLE_ADDRESS_SPACE;
-
/* Tell the highlevel this host is ready */
if (hpsb_add_host(host))
FAIL(-ENOMEM, "Failed to register host with highlevel");
case OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE:
/* The ohci_soft_reset() stops all DMA contexts, so we
* dont need to do this. */
+ /* Free AR dma */
free_dma_rcv_ctx(&ohci->ar_req_context);
free_dma_rcv_ctx(&ohci->ar_resp_context);
+
+ /* Free AT dma */
free_dma_trm_ctx(&ohci->at_req_context);
free_dma_trm_ctx(&ohci->at_resp_context);
+
+ /* Free IR dma */
free_dma_rcv_ctx(&ohci->ir_legacy_context);
+
+ /* Free IT dma */
free_dma_trm_ctx(&ohci->it_legacy_context);
+ /* Free IR legacy dma */
+ free_dma_rcv_ctx(&ohci->ir_legacy_context);
+
+
case OHCI_INIT_HAVE_SELFID_BUFFER:
pci_free_consistent(ohci->dev, OHCI1394_SI_DMA_BUF_SIZE,
ohci->selfid_buf_cpu,
static int ohci1394_pci_resume (struct pci_dev *pdev)
{
#ifdef CONFIG_PPC_PMAC
- if (machine_is(powermac)) {
+ if (_machine == _MACH_Pmac) {
struct device_node *of_node;
/* Re-enable 1394 */
pci_save_state(pdev);
#ifdef CONFIG_PPC_PMAC
- if (machine_is(powermac)) {
+ if (_machine == _MACH_Pmac) {
struct device_node *of_node;
/* Disable 1394 */