This commit was manufactured by cvs2svn to create branch 'vserver'.
[linux-2.6.git] / drivers / infiniband / hw / mthca / mthca_av.c
diff --git a/drivers/infiniband/hw/mthca/mthca_av.c b/drivers/infiniband/hw/mthca/mthca_av.c
new file mode 100644 (file)
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--- /dev/null
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+/*
+ * Copyright (c) 2004 Topspin Communications.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * $Id: mthca_av.c 1349 2004-12-16 21:09:43Z roland $
+ */
+
+#include <linux/init.h>
+
+#include <ib_verbs.h>
+#include <ib_cache.h>
+
+#include "mthca_dev.h"
+
+struct mthca_av {
+       u32 port_pd;
+       u8  reserved1;
+       u8  g_slid;
+       u16 dlid;
+       u8  reserved2;
+       u8  gid_index;
+       u8  msg_sr;
+       u8  hop_limit;
+       u32 sl_tclass_flowlabel;
+       u32 dgid[4];
+};
+
+int mthca_create_ah(struct mthca_dev *dev,
+                   struct mthca_pd *pd,
+                   struct ib_ah_attr *ah_attr,
+                   struct mthca_ah *ah)
+{
+       u32 index = -1;
+       struct mthca_av *av = NULL;
+
+       ah->on_hca = 0;
+
+       if (!atomic_read(&pd->sqp_count) &&
+           !(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
+               index = mthca_alloc(&dev->av_table.alloc);
+
+               /* fall back to allocate in host memory */
+               if (index == -1)
+                       goto host_alloc;
+
+               av = kmalloc(sizeof *av, GFP_KERNEL);
+               if (!av)
+                       goto host_alloc;
+
+               ah->on_hca = 1;
+               ah->avdma  = dev->av_table.ddr_av_base +
+                       index * MTHCA_AV_SIZE;
+       }
+
+ host_alloc:
+       if (!ah->on_hca) {
+               ah->av = pci_pool_alloc(dev->av_table.pool,
+                                       SLAB_KERNEL, &ah->avdma);
+               if (!ah->av)
+                       return -ENOMEM;
+
+               av = ah->av;
+       }
+
+       ah->key = pd->ntmr.ibmr.lkey;
+
+       memset(av, 0, MTHCA_AV_SIZE);
+
+       av->port_pd = cpu_to_be32(pd->pd_num | (ah_attr->port_num << 24));
+       av->g_slid  = ah_attr->src_path_bits;
+       av->dlid    = cpu_to_be16(ah_attr->dlid);
+       av->msg_sr  = (3 << 4) | /* 2K message */
+               ah_attr->static_rate;
+       av->sl_tclass_flowlabel = cpu_to_be32(ah_attr->sl << 28);
+       if (ah_attr->ah_flags & IB_AH_GRH) {
+               av->g_slid |= 0x80;
+               av->gid_index = (ah_attr->port_num - 1) * dev->limits.gid_table_len +
+                       ah_attr->grh.sgid_index;
+               av->hop_limit = ah_attr->grh.hop_limit;
+               av->sl_tclass_flowlabel |=
+                       cpu_to_be32((ah_attr->grh.traffic_class << 20) |
+                                   ah_attr->grh.flow_label);
+               memcpy(av->dgid, ah_attr->grh.dgid.raw, 16);
+       } else {
+               /* Arbel workaround -- low byte of GID must be 2 */
+               av->dgid[3] = cpu_to_be32(2);
+       }
+
+       if (0) {
+               int j;
+
+               mthca_dbg(dev, "Created UDAV at %p/%08lx:\n",
+                         av, (unsigned long) ah->avdma);
+               for (j = 0; j < 8; ++j)
+                       printk(KERN_DEBUG "  [%2x] %08x\n",
+                              j * 4, be32_to_cpu(((u32 *) av)[j]));
+       }
+
+       if (ah->on_hca) {
+               memcpy_toio(dev->av_table.av_map + index * MTHCA_AV_SIZE,
+                           av, MTHCA_AV_SIZE);
+               kfree(av);
+       }
+
+       return 0;
+}
+
+int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah)
+{
+       if (ah->on_hca)
+               mthca_free(&dev->av_table.alloc,
+                          (ah->avdma - dev->av_table.ddr_av_base) /
+                          MTHCA_AV_SIZE);
+       else
+               pci_pool_free(dev->av_table.pool, ah->av, ah->avdma);
+
+       return 0;
+}
+
+int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
+                 struct ib_ud_header *header)
+{
+       if (ah->on_hca)
+               return -EINVAL;
+
+       header->lrh.service_level   = be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 28;
+       header->lrh.destination_lid = ah->av->dlid;
+       header->lrh.source_lid      = ah->av->g_slid & 0x7f;
+       if (ah->av->g_slid & 0x80) {
+               header->grh_present = 1;
+               header->grh.traffic_class =
+                       (be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 20) & 0xff;
+               header->grh.flow_label    =
+                       ah->av->sl_tclass_flowlabel & cpu_to_be32(0xfffff);
+               ib_get_cached_gid(&dev->ib_dev,
+                                 be32_to_cpu(ah->av->port_pd) >> 24,
+                                 ah->av->gid_index,
+                                 &header->grh.source_gid);
+               memcpy(header->grh.destination_gid.raw,
+                      ah->av->dgid, 16);
+       } else {
+               header->grh_present = 0;
+       }
+
+       return 0;
+}
+
+int __devinit mthca_init_av_table(struct mthca_dev *dev)
+{
+       int err;
+
+       err = mthca_alloc_init(&dev->av_table.alloc,
+                              dev->av_table.num_ddr_avs,
+                              dev->av_table.num_ddr_avs - 1,
+                              0);
+       if (err)
+               return err;
+
+       dev->av_table.pool = pci_pool_create("mthca_av", dev->pdev,
+                                            MTHCA_AV_SIZE,
+                                            MTHCA_AV_SIZE, 0);
+       if (!dev->av_table.pool)
+               goto out_free_alloc;
+
+       if (!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
+               dev->av_table.av_map = ioremap(pci_resource_start(dev->pdev, 4) +
+                                              dev->av_table.ddr_av_base -
+                                              dev->ddr_start,
+                                              dev->av_table.num_ddr_avs *
+                                              MTHCA_AV_SIZE);
+               if (!dev->av_table.av_map)
+                       goto out_free_pool;
+       } else
+               dev->av_table.av_map = NULL;
+
+       return 0;
+
+ out_free_pool:
+       pci_pool_destroy(dev->av_table.pool);
+
+ out_free_alloc:
+       mthca_alloc_cleanup(&dev->av_table.alloc);
+       return -ENOMEM;
+}
+
+void __devexit mthca_cleanup_av_table(struct mthca_dev *dev)
+{
+       if (dev->av_table.av_map)
+               iounmap(dev->av_table.av_map);
+       pci_pool_destroy(dev->av_table.pool);
+       mthca_alloc_cleanup(&dev->av_table.alloc);
+}