#if defined(DIVA_IDI_RX_DMA)
DIVA_XDI_EXTENDED_FEATURE_CMA |
DIVA_XDI_EXTENDED_FEATURE_RX_DMA |
+ DIVA_XDI_EXTENDED_FEATURE_MANAGEMENT_DMA |
#endif
DIVA_XDI_EXTENDED_FEATURE_NO_CANCEL_RC),
0
if (pI->descriptor_number >= 0) {
dword dma_magic;
void* local_addr;
+#if 0
DBG_TRC(("A(%d) dma_alloc(%d)",
IoAdapter->ANum, pI->descriptor_number))
+#endif
diva_get_dma_map_entry (\
(struct _diva_dma_map_entry*)IoAdapter->dma_map,
pI->descriptor_number,
}
} else if ((pI->operation == IDI_SYNC_REQ_DMA_DESCRIPTOR_FREE) &&
(pI->descriptor_number >= 0)) {
+#if 0
DBG_TRC(("A(%d) dma_free(%d)", IoAdapter->ANum, pI->descriptor_number))
+#endif
diva_free_dma_map_entry((struct _diva_dma_map_entry*)IoAdapter->dma_map,
pI->descriptor_number);
pI->descriptor_number = -1;
&syncReq->xdi_logical_adapter_number.info;
pI->logical_adapter_number = IoAdapter->ANum;
pI->controller = IoAdapter->ControllerNumber;
+ pI->total_controllers = IoAdapter->Properties.Adapters;
} return;
case IDI_SYNC_REQ_XDI_GET_CAPI_PARAMS: {
diva_xdi_get_capi_parameters_t prms, *pI = &syncReq->xdi_capi_prms.info;
}
syncReq->GetSerial.serial = 0 ;
break ;
+ case IDI_SYNC_REQ_GET_CARDTYPE:
+ if ( IoAdapter )
+ {
+ syncReq->GetCardType.cardtype = IoAdapter->cardType ;
+ DBG_TRC(("xdi: Adapter %d / CardType %ld",
+ IoAdapter->ANum, IoAdapter->cardType))
+ return ;
+ }
+ syncReq->GetCardType.cardtype = 0 ;
+ break ;
case IDI_SYNC_REQ_GET_XLOG:
if ( IoAdapter )
{
}
e->Ind = 0 ;
break ;
+ case IDI_SYNC_REQ_GET_DBG_XLOG:
+ if ( IoAdapter )
+ {
+ pcm_req (IoAdapter, e) ;
+ return ;
+ }
+ e->Ind = 0 ;
+ break ;
case IDI_SYNC_REQ_GET_FEATURES:
if ( IoAdapter )
{
}
if ( IoAdapter )
{
+#if 0
DBG_FTL(("xdi: unknown Req 0 / Rc %d !", e->Rc))
+#endif
return ;
}
}
diva_os_enter_spin_lock (&IoAdapter->data_spin_lock,
&OldIrql,
"data_pcm_1");
- IoAdapter->pcm_data = (unsigned long)pcm;
+ IoAdapter->pcm_data = (void *)pcm;
IoAdapter->pcm_pending = 1;
diva_os_schedule_soft_isr (&IoAdapter->req_soft_isr);
diva_os_leave_spin_lock (&IoAdapter->data_spin_lock,
&OldIrql,
"data_pcm_3");
IoAdapter->pcm_pending = 0;
- IoAdapter->pcm_data = 0;
+ IoAdapter->pcm_data = NULL ;
diva_os_leave_spin_lock (&IoAdapter->data_spin_lock,
&OldIrql,
"data_pcm_3");
&OldIrql,
"data_pcm_4");
IoAdapter->pcm_pending = 0;
- IoAdapter->pcm_data = 0;
+ IoAdapter->pcm_data = NULL ;
diva_os_leave_spin_lock (&IoAdapter->data_spin_lock,
&OldIrql,
"data_pcm_4");
void io_in_buffer(ADAPTER * a, void * adr, void * buffer, word len)
{
byte *Port = (byte*)DIVA_OS_MEM_ATTACH_PORT((PISDN_ADAPTER)a->io);
- byte* P = (byte*)buffer;
+ byte* P = (byte*)buffer;
if ((long)adr & 1) {
outppw(Port+4, (word)(unsigned long)adr);
*P = inpp(Port);
if (!len) {
DIVA_OS_MEM_DETACH_PORT((PISDN_ADAPTER)a->io, Port);
return;
- }
+ }
}
outppw(Port+4, (word)(unsigned long)adr);
inppw_buffer (Port, P, len+1);
void io_out_buffer(ADAPTER * a, void * adr, void * buffer, word len)
{
byte *Port = (byte*)DIVA_OS_MEM_ATTACH_PORT((PISDN_ADAPTER)a->io);
- byte* P = (byte*)buffer;
+ byte* P = (byte*)buffer;
if ((long)adr & 1) {
outppw(Port+4, (word)(unsigned long)adr);
outpp(Port, *P);
/* --------------------------------------------------------------------------
routines for aligned reading and writing on RISC
-------------------------------------------------------------------------- */
-void outp_words_from_buffer (word* adr, byte* P, word len)
+void outp_words_from_buffer (word* adr, byte* P, dword len)
{
- word i = 0;
+ dword i = 0;
word w;
- while (i < (len & 0xfffe)) {
+ while (i < (len & 0xfffffffe)) {
w = P[i++];
w += (P[i++])<<8;
outppw (adr, w);
}
}
-void inp_words_to_buffer (word* adr, byte* P, word len)
+void inp_words_to_buffer (word* adr, byte* P, dword len)
{
- word i = 0;
+ dword i = 0;
word w;
- while (i < (len & 0xfffe)) {
+ while (i < (len & 0xfffffffe)) {
w = inppw (adr);
P[i++] = (byte)(w);
P[i++] = (byte)(w>>8);