{
struct saa7146_vv *vv = dev->vv_data;
- u32 *cpu;
- dma_addr_t dma_addr;
-
+ u32 *cpu;
+ dma_addr_t dma_addr;
+
int count = 0;
int i;
DECLARE_WAITQUEUE(wait, current);
-
+
DEB_VBI(("dev:%p\n",dev));
-
+
/* once again, a bug in the saa7146: the brs acquisition
is buggy and especially the BXO-counter does not work
as specified. there is this workaround, but please
saa7146_write(dev, BASE_EVEN3, dma_addr);
saa7146_write(dev, BASE_ODD3, dma_addr+vbi_pixel_to_capture);
saa7146_write(dev, PROT_ADDR3, dma_addr+4096);
- saa7146_write(dev, PITCH3, vbi_pixel_to_capture);
+ saa7146_write(dev, PITCH3, vbi_pixel_to_capture);
saa7146_write(dev, BASE_PAGE3, 0x0);
saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0));
saa7146_write(dev, MC2, MASK_04|MASK_20);
- /* load brs-control register */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
- /* BXO = 1h, BRS to outbound */
- WRITE_RPS1(0xc000008c);
+ /* load brs-control register */
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
+ /* BXO = 1h, BRS to outbound */
+ WRITE_RPS1(0xc000008c);
/* wait for vbi_a or vbi_b*/
if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
DEB_D(("...using port b\n"));
DEB_D(("...using port a\n"));
WRITE_RPS1(CMD_PAUSE | MASK_10);
}
- /* upload brs */
- WRITE_RPS1(CMD_UPLOAD | MASK_08);
- /* load brs-control register */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
- /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
- WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19);
- /* wait for brs_done */
- WRITE_RPS1(CMD_PAUSE | MASK_08);
- /* upload brs */
- WRITE_RPS1(CMD_UPLOAD | MASK_08);
- /* load video-dma3 NumLines3 and NumBytes3 */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4));
- /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
- WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture));
- /* load brs-control register */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
- /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
- WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start
- /* wait for brs_done */
- WRITE_RPS1(CMD_PAUSE | MASK_08);
- /* upload brs and video-dma3*/
- WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04);
- /* load mc2 register: enable dma3 */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
- WRITE_RPS1(MASK_20 | MASK_04);
- /* generate interrupt */
- WRITE_RPS1(CMD_INTERRUPT);
- /* stop rps1 */
- WRITE_RPS1(CMD_STOP);
-
+ /* upload brs */
+ WRITE_RPS1(CMD_UPLOAD | MASK_08);
+ /* load brs-control register */
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
+ /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
+ WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19);
+ /* wait for brs_done */
+ WRITE_RPS1(CMD_PAUSE | MASK_08);
+ /* upload brs */
+ WRITE_RPS1(CMD_UPLOAD | MASK_08);
+ /* load video-dma3 NumLines3 and NumBytes3 */
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4));
+ /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
+ WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture));
+ /* load brs-control register */
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
+ /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
+ WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start
+ /* wait for brs_done */
+ WRITE_RPS1(CMD_PAUSE | MASK_08);
+ /* upload brs and video-dma3*/
+ WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04);
+ /* load mc2 register: enable dma3 */
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
+ WRITE_RPS1(MASK_20 | MASK_04);
+ /* generate interrupt */
+ WRITE_RPS1(CMD_INTERRUPT);
+ /* stop rps1 */
+ WRITE_RPS1(CMD_STOP);
+
/* we have to do the workaround twice to be sure that
everything is ok */
for(i = 0; i < 2; i++) {
saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0));
saa7146_write(dev, MC2, MASK_04|MASK_20);
-
+
/* enable rps1 irqs */
- IER_ENABLE(dev,MASK_28);
+ SAA7146_IER_ENABLE(dev,MASK_28);
/* prepare to wait to be woken up by the irq-handler */
add_wait_queue(&vv->vbi_wq, &wait);
/* start rps1 to enable workaround */
saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
- saa7146_write(dev, MC1, (MASK_13 | MASK_29));
-
+ saa7146_write(dev, MC1, (MASK_13 | MASK_29));
+
schedule();
DEB_VBI(("brs bug workaround %d/1.\n",i));
-
+
remove_wait_queue(&vv->vbi_wq, &wait);
current->state = TASK_RUNNING;
/* disable rps1 irqs */
- IER_DISABLE(dev,MASK_28);
+ SAA7146_IER_DISABLE(dev,MASK_28);
/* stop video-dma3 */
saa7146_write(dev, MC1, MASK_20);
if(signal_pending(current)) {
-
+
DEB_VBI(("aborted (rps:0x%08x).\n",saa7146_read(dev,RPS_ADDR1)));
/* stop rps1 for sure */
return 0;
}
-void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
+static void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
{
struct saa7146_vv *vv = dev->vv_data;
vdma3.pitch = vbi_pixel_to_capture;
vdma3.base_page = buf->pt[2].dma | ME1;
vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture;
+
saa7146_write_out_dma(dev, 3, &vdma3);
/* write beginning of rps-program */
capture and might cause that the first buffer is only half filled (with only
one field). but since this is some sort of streaming data, this is not that negative.
but by doing this, we can use the whole engine from video-buf.c... */
-
+
/*
WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait);
WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait);
*/
/* set bit 1 */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4));
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4));
WRITE_RPS1(MASK_28 | MASK_12);
-
+
/* turn on video-dma3 */
- WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4));
- WRITE_RPS1(MASK_04 | MASK_20); /* => mask */
+ WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4));
+ WRITE_RPS1(MASK_04 | MASK_20); /* => mask */
WRITE_RPS1(MASK_04 | MASK_20); /* => values */
-
+
/* wait for o_fid_a/b / e_fid_a/b toggle */
WRITE_RPS1(CMD_PAUSE | o_wait);
WRITE_RPS1(CMD_PAUSE | e_wait);
/* generate interrupt */
- WRITE_RPS1(CMD_INTERRUPT);
+ WRITE_RPS1(CMD_INTERRUPT);
/* stop */
- WRITE_RPS1(CMD_STOP);
+ WRITE_RPS1(CMD_STOP);
/* enable rps1 irqs */
- IER_ENABLE(dev, MASK_28);
+ SAA7146_IER_ENABLE(dev, MASK_28);
/* write the address of the rps-program */
saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
/* turn on rps */
- saa7146_write(dev, MC1, (MASK_13 | MASK_29));
+ saa7146_write(dev, MC1, (MASK_13 | MASK_29));
}
static int buffer_activate(struct saa7146_dev *dev,
return 0;
}
-static int buffer_prepare(struct file *file, struct videobuf_buffer *vb,enum v4l2_field field)
+static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,enum v4l2_field field)
{
+ struct file *file = q->priv_data;
struct saa7146_fh *fh = file->private_data;
struct saa7146_dev *dev = fh->dev;
struct saa7146_buf *buf = (struct saa7146_buf *)vb;
size = lines * llength;
DEB_VBI(("vb:%p\n",vb));
-
+
if (0 != buf->vb.baddr && buf->vb.bsize < size) {
DEB_VBI(("size mismatch.\n"));
return -EINVAL;
}
-
+
if (buf->vb.size != size)
- saa7146_dma_free(dev,buf);
+ saa7146_dma_free(dev,q,buf);
if (STATE_NEEDS_INIT == buf->vb.state) {
buf->vb.width = llength;
saa7146_pgtable_free(dev->pci, &buf->pt[2]);
saa7146_pgtable_alloc(dev->pci, &buf->pt[2]);
- err = videobuf_iolock(dev->pci,&buf->vb,NULL);
+ err = videobuf_iolock(q,&buf->vb, NULL);
if (err)
goto oops;
err = saa7146_pgtable_build_single(dev->pci, &buf->pt[2], buf->vb.dma.sglist, buf->vb.dma.sglen);
oops:
DEB_VBI(("error out.\n"));
- saa7146_dma_free(dev,buf);
+ saa7146_dma_free(dev,q,buf);
return err;
}
-static int buffer_setup(struct file *file, unsigned int *count, unsigned int *size)
+static int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size)
{
int llength,lines;
-
+
lines = 16 * 2 ; /* 2 fields */
llength = vbi_pixel_to_capture;
return 0;
}
-static void buffer_queue(struct file *file, struct videobuf_buffer *vb)
+static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
{
+ struct file *file = q->priv_data;
struct saa7146_fh *fh = file->private_data;
struct saa7146_dev *dev = fh->dev;
struct saa7146_vv *vv = dev->vv_data;
struct saa7146_buf *buf = (struct saa7146_buf *)vb;
-
+
DEB_VBI(("vb:%p\n",vb));
saa7146_buffer_queue(dev,&vv->vbi_q,buf);
}
-static void buffer_release(struct file *file, struct videobuf_buffer *vb)
+static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
{
+ struct file *file = q->priv_data;
struct saa7146_fh *fh = file->private_data;
struct saa7146_dev *dev = fh->dev;
struct saa7146_buf *buf = (struct saa7146_buf *)vb;
-
+
DEB_VBI(("vb:%p\n",vb));
- saa7146_dma_free(dev,buf);
+ saa7146_dma_free(dev,q,buf);
}
static struct videobuf_queue_ops vbi_qops = {
struct saa7146_vv *vv = dev->vv_data;
unsigned long flags;
DEB_VBI(("dev:%p, fh:%p\n",dev, fh));
-
+
spin_lock_irqsave(&dev->slock,flags);
/* disable rps1 */
saa7146_write(dev, MC1, MASK_29);
/* disable rps1 irqs */
- IER_DISABLE(dev, MASK_28);
+ SAA7146_IER_DISABLE(dev, MASK_28);
/* shut down dma 3 transfers */
saa7146_write(dev, MC1, MASK_20);
saa7146_buffer_finish(dev,&vv->vbi_q,STATE_DONE);
}
- videobuf_queue_cancel(file,&fh->vbi_q);
+ videobuf_queue_cancel(&fh->vbi_q);
vv->vbi_streaming = NULL;
struct file *file = (struct file*)data;
struct saa7146_fh *fh = file->private_data;
struct saa7146_dev *dev = fh->dev;
-
+
DEB_VBI(("dev:%p, fh:%p\n",dev, fh));
vbi_stop(fh, file);
static int vbi_open(struct saa7146_dev *dev, struct file *file)
{
struct saa7146_fh *fh = (struct saa7146_fh *)file->private_data;
-
+
u32 arbtr_ctrl = saa7146_read(dev, PCI_BT_V1);
int ret = 0;
-
+
DEB_VBI(("dev:%p, fh:%p\n",dev,fh));
ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS);
arbtr_ctrl &= ~0x1f0000;
arbtr_ctrl |= 0x1d0000;
saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
- saa7146_write(dev, MC2, (MASK_04|MASK_20));
-
+ saa7146_write(dev, MC2, (MASK_04|MASK_20));
+
memset(&fh->vbi_fmt,0,sizeof(fh->vbi_fmt));
fh->vbi_fmt.sampling_rate = 27000000;
- fh->vbi_fmt.offset = 248; /* todo */
+ fh->vbi_fmt.offset = 248; /* todo */
fh->vbi_fmt.samples_per_line = vbi_pixel_to_capture;
fh->vbi_fmt.sample_format = V4L2_PIX_FMT_GREY;
dev->pci, &dev->slock,
V4L2_BUF_TYPE_VBI_CAPTURE,
V4L2_FIELD_SEQ_TB, // FIXME: does this really work?
- sizeof(struct saa7146_buf));
- init_MUTEX(&fh->vbi_q.lock);
+ sizeof(struct saa7146_buf),
+ file);
+ mutex_init(&fh->vbi_q.lock);
init_timer(&fh->vbi_read_timeout);
fh->vbi_read_timeout.function = vbi_read_timeout;
}
/* upload brs register */
- saa7146_write(dev, MC2, (MASK_08|MASK_24));
+ saa7146_write(dev, MC2, (MASK_08|MASK_24));
return 0;
}
spin_unlock(&dev->slock);
}
-static ssize_t vbi_read(struct file *file, char *data, size_t count, loff_t *ppos)
+static ssize_t vbi_read(struct file *file, char __user *data, size_t count, loff_t *ppos)
{
struct saa7146_fh *fh = file->private_data;
struct saa7146_dev *dev = fh->dev;
ssize_t ret = 0;
DEB_VBI(("dev:%p, fh:%p\n",dev,fh));
-
+
if( NULL == vv->vbi_streaming ) {
// fixme: check if dma3 is available
// fixme: activate vbi engine here if necessary. (really?)
}
mod_timer(&fh->vbi_read_timeout, jiffies+BUFFER_TIMEOUT);
- ret = videobuf_read_stream(file, &fh->vbi_q, data, count, ppos, 1);
+ ret = videobuf_read_stream(&fh->vbi_q, data, count, ppos, 1,
+ file->f_flags & O_NONBLOCK);
/*
printk("BASE_ODD3: 0x%08x\n", saa7146_read(dev, BASE_ODD3));
printk("BASE_EVEN3: 0x%08x\n", saa7146_read(dev, BASE_EVEN3));
}
struct saa7146_use_ops saa7146_vbi_uops = {
- .init = vbi_init,
- .open = vbi_open,
+ .init = vbi_init,
+ .open = vbi_open,
.release = vbi_close,
.irq_done = vbi_irq_done,
- .read = vbi_read,
+ .read = vbi_read,
};
git://git.onelab.eu / linux-2.6.git / blobdiff