/*
VES1820 - Single Chip Cable Channel Receiver driver module
+ used on the the Siemens DVB-C cards
Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
-#include <asm/div64.h>
#include "dvb_frontend.h"
-#include "ves1820.h"
+#include "dvb_functions.h"
+#if 0
+#define dprintk(x...) printk(x)
+#else
+#define dprintk(x...)
+#endif
-struct ves1820_state {
-
- struct i2c_adapter *i2c;
-
- struct dvb_frontend_ops ops;
-
- /* configuration settings */
- const struct ves1820_config* config;
-
- struct dvb_frontend frontend;
+#define MAX_UNITS 4
+static int pwm[MAX_UNITS] = { -1, -1, -1, -1 };
+static int verbose;
- /* private demodulator data */
- u8 reg0;
- u8 pwm;
+/**
+ * since we need only a few bits to store internal state we don't allocate
+ * extra memory but use frontend->data as bitfield
+ */
+
+#define SET_PWM(data,pwm) do { \
+ long d = (long)data; \
+ d &= ~0xff; \
+ d |= pwm; \
+ data = (void *)d; \
+} while (0)
+
+#define SET_REG0(data,reg0) do { \
+ long d = (long)data; \
+ d &= ~(0xff << 8); \
+ d |= reg0 << 8; \
+ data = (void *)d; \
+} while (0)
+
+#define SET_TUNER(data,type) do { \
+ long d = (long)data; \
+ d &= ~(0xff << 16); \
+ d |= type << 16; \
+ data = (void *)d; \
+} while (0)
+
+#define SET_DEMOD_ADDR(data,type) do { \
+ long d = (long)data; \
+ d &= ~(0xff << 24); \
+ d |= type << 24; \
+ data = (void *)d; \
+} while (0)
+
+#define GET_PWM(data) ((u8) ((long) data & 0xff))
+#define GET_REG0(data) ((u8) (((long) data >> 8) & 0xff))
+#define GET_TUNER(data) ((u8) (((long) data >> 16) & 0xff))
+#define GET_DEMOD_ADDR(data) ((u8) (((long) data >> 24) & 0xff))
+
+#if defined(CONFIG_DBOX2)
+#define XIN 69600000UL
+#define DISABLE_INVERSION(reg0) do { reg0 &= ~0x20; } while (0)
+#define ENABLE_INVERSION(reg0) do { reg0 |= 0x20; } while (0)
+#define HAS_INVERSION(reg0) (reg0 & 0x20)
+#else /* PCI cards */
+#define XIN 57840000UL
+#define DISABLE_INVERSION(reg0) do { reg0 |= 0x20; } while (0)
+#define ENABLE_INVERSION(reg0) do { reg0 &= ~0x20; } while (0)
+#define HAS_INVERSION(reg0) (!(reg0 & 0x20))
+#endif
+
+#define FIN (XIN >> 4)
+
+
+
+static struct dvb_frontend_info ves1820_info = {
+ .name = "VES1820 based DVB-C frontend",
+ .type = FE_QAM,
+ .frequency_stepsize = 62500,
+ .frequency_min = 51000000,
+ .frequency_max = 858000000,
+ .symbol_rate_min = (XIN/2)/64, /* SACLK/64 == (XIN/2)/64 */
+ .symbol_rate_max = (XIN/2)/4, /* SACLK/4 */
+#if 0
+ .frequency_tolerance = ???,
+ .symbol_rate_tolerance = ???, /* ppm */ /* == 8% (spec p. 5) */
+ .notifier_delay = ?,
+#endif
+ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
+ FE_CAN_QAM_128 | FE_CAN_QAM_256 |
+ FE_CAN_FEC_AUTO | FE_CAN_INVERSION_AUTO,
};
-static int verbose;
-static u8 ves1820_inittab[] = {
- 0x69, 0x6A, 0x93, 0x12, 0x12, 0x46, 0x26, 0x1A,
+static u8 ves1820_inittab [] =
+{
+ 0x69, 0x6A, 0x9B, 0x12, 0x12, 0x46, 0x26, 0x1A,
0x43, 0x6A, 0xAA, 0xAA, 0x1E, 0x85, 0x43, 0x20,
0xE0, 0x00, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x40
};
-static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
+
+static int ves1820_writereg (struct dvb_frontend *fe, u8 reg, u8 data)
{
+ u8 addr = GET_DEMOD_ADDR(fe->data);
u8 buf[] = { 0x00, reg, data };
- struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };
+ struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 };
+ struct dvb_i2c_bus *i2c = fe->i2c;
int ret;
- ret = i2c_transfer(state->i2c, &msg, 1);
+ ret = i2c->xfer (i2c, &msg, 1);
if (ret != 1)
- printk("ves1820: %s(): writereg error (reg == 0x%02x,"
- "val == 0x%02x, ret == %i)\n", __FUNCTION__, reg, data, ret);
+ printk("DVB: VES1820(%d): %s, writereg error "
+ "(reg == 0x%02x, val == 0x%02x, ret == %i)\n",
+ fe->i2c->adapter->num, __FUNCTION__, reg, data, ret);
- msleep(10);
+ dvb_delay(10);
return (ret != 1) ? -EREMOTEIO : 0;
}
-static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)
+
+static u8 ves1820_readreg (struct dvb_frontend *fe, u8 reg)
{
u8 b0 [] = { 0x00, reg };
u8 b1 [] = { 0 };
- struct i2c_msg msg[] = {
- {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},
- {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
- };
+ u8 addr = GET_DEMOD_ADDR(fe->data);
+ struct i2c_msg msg [] = { { .addr = addr, .flags = 0, .buf = b0, .len = 2 },
+ { .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
+ struct dvb_i2c_bus *i2c = fe->i2c;
int ret;
- ret = i2c_transfer(state->i2c, msg, 2);
+ ret = i2c->xfer (i2c, msg, 2);
if (ret != 2)
- printk("ves1820: %s(): readreg error (reg == 0x%02x,"
- "ret == %i)\n", __FUNCTION__, reg, ret);
+ printk("DVB: VES1820(%d): %s: readreg error (ret == %i)\n",
+ fe->i2c->adapter->num, __FUNCTION__, ret);
return b1[0];
}
-static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversion)
+static int tuner_write (struct dvb_i2c_bus *i2c, u8 addr, u8 data [4])
{
- reg0 |= state->reg0 & 0x62;
+ int ret;
+ struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = data, .len = 4 };
+
+ ret = i2c->xfer (i2c, &msg, 1);
+
+ if (ret != 1)
+ printk("DVB: VES1820(%d): %s: i/o error (ret == %i)\n",
+ i2c->adapter->num, __FUNCTION__, ret);
+
+ return (ret != 1) ? -EREMOTEIO : 0;
+}
+
+
+/**
+ * set up the downconverter frequency divisor for a
+ * reference clock comparision frequency of 62.5 kHz.
+ */
+static int tuner_set_tv_freq (struct dvb_frontend *fe, u32 freq)
+{
+ u32 div, ifreq;
+ static u8 addr [] = { 0x61, 0x62 };
+ static u8 byte3 [] = { 0x8e, 0x85 };
+ int tuner_type = GET_TUNER(fe->data);
+ u8 buf [4];
+
+ if (tuner_type == 0xff) /* PLL not reachable over i2c ... */
+ return 0;
+
+ if (strstr (fe->i2c->adapter->name, "Technotrend") ||
+ strstr (fe->i2c->adapter->name, "TT-Budget"))
+ ifreq = 35937500;
+ else
+ ifreq = 36125000;
+
+ div = (freq + ifreq + 31250) / 62500;
+
+ buf[0] = (div >> 8) & 0x7f;
+ buf[1] = div & 0xff;
+ buf[2] = byte3[tuner_type];
+
+ if (tuner_type == 1) {
+ buf[2] |= (div >> 10) & 0x60;
+ buf[3] = (freq < 174000000 ? 0x88 :
+ freq < 470000000 ? 0x84 : 0x81);
+ } else {
+ buf[3] = (freq < 174000000 ? 0xa1 :
+ freq < 454000000 ? 0x92 : 0x34);
+ }
+
+ return tuner_write (fe->i2c, addr[tuner_type], buf);
+}
+
+
+static int ves1820_setup_reg0 (struct dvb_frontend *fe, u8 reg0,
+ fe_spectral_inversion_t inversion)
+{
+ reg0 |= GET_REG0(fe->data) & 0x62;
- if (INVERSION_ON == inversion) {
- if (!state->config->invert) reg0 |= 0x20;
- else reg0 &= ~0x20;
+ if (INVERSION_ON == inversion)
+ ENABLE_INVERSION(reg0);
+ else if (INVERSION_OFF == inversion)
+ DISABLE_INVERSION(reg0);
- } else if (INVERSION_OFF == inversion) {
-
- if (!state->config->invert) reg0 &= ~0x20;
- else reg0 |= 0x20;
+ ves1820_writereg (fe, 0x00, reg0 & 0xfe);
+ ves1820_writereg (fe, 0x00, reg0 | 0x01);
+
+ /**
+ * check lock and toggle inversion bit if required...
+ */
+ if (INVERSION_AUTO == inversion && !(ves1820_readreg (fe, 0x11) & 0x08)) {
+ mdelay(50);
+ if (!(ves1820_readreg (fe, 0x11) & 0x08)) {
+ reg0 ^= 0x20;
+ ves1820_writereg (fe, 0x00, reg0 & 0xfe);
+ ves1820_writereg (fe, 0x00, reg0 | 0x01);
+ }
}
- ves1820_writereg(state, 0x00, reg0 & 0xfe);
- ves1820_writereg(state, 0x00, reg0 | 0x01);
+ SET_REG0(fe->data, reg0);
+
+ return 0;
+}
+
- state->reg0 = reg0;
+static int ves1820_init (struct dvb_frontend *fe)
+{
+ int i;
+
+ dprintk("DVB: VES1820(%d): init chip\n", fe->i2c->adapter->num);
+
+ ves1820_writereg (fe, 0, 0);
+
+#if defined(CONFIG_DBOX2)
+ ves1820_inittab[2] &= ~0x08;
+#endif
+
+ for (i=0; i<53; i++)
+ ves1820_writereg (fe, i, ves1820_inittab[i]);
+
+ ves1820_writereg (fe, 0x34, GET_PWM(fe->data));
return 0;
}
-static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)
+
+static int ves1820_set_symbolrate (struct dvb_frontend *fe, u32 symbolrate)
{
s32 BDR;
s32 BDRI;
s16 SFIL=0;
u16 NDEC = 0;
- u32 ratio;
- u32 fin;
- u32 tmp;
- u64 fptmp;
- u64 fpxin;
+ u32 tmp, ratio;
- if (symbolrate > state->config->xin / 2)
- symbolrate = state->config->xin / 2;
+ if (symbolrate > XIN/2)
+ symbolrate = XIN/2;
if (symbolrate < 500000)
symbolrate = 500000;
- if (symbolrate < state->config->xin / 16)
- NDEC = 1;
- if (symbolrate < state->config->xin / 32)
- NDEC = 2;
- if (symbolrate < state->config->xin / 64)
- NDEC = 3;
-
- /* yeuch! */
- fpxin = state->config->xin * 10;
- fptmp = fpxin; do_div(fptmp, 123);
- if (symbolrate < fptmp);
- SFIL = 1;
- fptmp = fpxin; do_div(fptmp, 160);
- if (symbolrate < fptmp);
- SFIL = 0;
- fptmp = fpxin; do_div(fptmp, 246);
- if (symbolrate < fptmp);
- SFIL = 1;
- fptmp = fpxin; do_div(fptmp, 320);
- if (symbolrate < fptmp);
- SFIL = 0;
- fptmp = fpxin; do_div(fptmp, 492);
- if (symbolrate < fptmp);
- SFIL = 1;
- fptmp = fpxin; do_div(fptmp, 640);
- if (symbolrate < fptmp);
- SFIL = 0;
- fptmp = fpxin; do_div(fptmp, 984);
- if (symbolrate < fptmp);
- SFIL = 1;
+ if (symbolrate < XIN/16) NDEC = 1;
+ if (symbolrate < XIN/32) NDEC = 2;
+ if (symbolrate < XIN/64) NDEC = 3;
+
+ if (symbolrate < (u32)(XIN/12.3)) SFIL = 1;
+ if (symbolrate < (u32)(XIN/16)) SFIL = 0;
+ if (symbolrate < (u32)(XIN/24.6)) SFIL = 1;
+ if (symbolrate < (u32)(XIN/32)) SFIL = 0;
+ if (symbolrate < (u32)(XIN/49.2)) SFIL = 1;
+ if (symbolrate < (u32)(XIN/64)) SFIL = 0;
+ if (symbolrate < (u32)(XIN/98.4)) SFIL = 1;
- fin = state->config->xin >> 4;
symbolrate <<= NDEC;
- ratio = (symbolrate << 4) / fin;
- tmp = ((symbolrate << 4) % fin) << 8;
- ratio = (ratio << 8) + tmp / fin;
- tmp = (tmp % fin) << 8;
- ratio = (ratio << 8) + (tmp + fin / 2) / fin;
+ ratio = (symbolrate << 4) / FIN;
+ tmp = ((symbolrate << 4) % FIN) << 8;
+ ratio = (ratio << 8) + tmp / FIN;
+ tmp = (tmp % FIN) << 8;
+ ratio = (ratio << 8) + (tmp + FIN/2) / FIN;
BDR = ratio;
- BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;
+ BDRI = (((XIN << 5) / symbolrate) + 1) / 2;
if (BDRI > 0xFF)
BDRI = 0xFF;
NDEC = (NDEC << 6) | ves1820_inittab[0x03];
- ves1820_writereg(state, 0x03, NDEC);
- ves1820_writereg(state, 0x0a, BDR & 0xff);
- ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
- ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
+ ves1820_writereg (fe, 0x03, NDEC);
+ ves1820_writereg (fe, 0x0a, BDR&0xff);
+ ves1820_writereg (fe, 0x0b, (BDR>> 8)&0xff);
+ ves1820_writereg (fe, 0x0c, (BDR>>16)&0x3f);
- ves1820_writereg(state, 0x0d, BDRI);
- ves1820_writereg(state, 0x0e, SFIL);
+ ves1820_writereg (fe, 0x0d, BDRI);
+ ves1820_writereg (fe, 0x0e, SFIL);
return 0;
}
-
-
-
-
-
-
-
-
-
-
-
-static int ves1820_init(struct dvb_frontend* fe)
+static int ves1820_set_parameters (struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
- int i;
- int val;
-
- ves1820_writereg(state, 0, 0);
-
- for (i = 0; i < 53; i++) {
- val = ves1820_inittab[i];
- if ((i == 2) && (state->config->selagc)) val |= 0x08;
- ves1820_writereg(state, i, val);
- }
-
- ves1820_writereg(state, 0x34, state->pwm);
-
- if (state->config->pll_init) state->config->pll_init(fe);
-
- return 0;
-}
-
-static int ves1820_set_parameters(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
-{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
static const u8 reg0x00 [] = { 0x00, 0x04, 0x08, 0x0c, 0x10 };
static const u8 reg0x01 [] = { 140, 140, 106, 100, 92 };
static const u8 reg0x05 [] = { 135, 100, 70, 54, 38 };
if (real_qam < 0 || real_qam > 4)
return -EINVAL;
- state->config->pll_set(fe, p);
- ves1820_set_symbolrate(state, p->u.qam.symbol_rate);
- ves1820_writereg(state, 0x34, state->pwm);
+ tuner_set_tv_freq (fe, p->frequency);
+ ves1820_set_symbolrate (fe, p->u.qam.symbol_rate);
+ ves1820_writereg (fe, 0x34, GET_PWM(fe->data));
+
+ ves1820_writereg (fe, 0x01, reg0x01[real_qam]);
+ ves1820_writereg (fe, 0x05, reg0x05[real_qam]);
+ ves1820_writereg (fe, 0x08, reg0x08[real_qam]);
+ ves1820_writereg (fe, 0x09, reg0x09[real_qam]);
- ves1820_writereg(state, 0x01, reg0x01[real_qam]);
- ves1820_writereg(state, 0x05, reg0x05[real_qam]);
- ves1820_writereg(state, 0x08, reg0x08[real_qam]);
- ves1820_writereg(state, 0x09, reg0x09[real_qam]);
+ ves1820_setup_reg0 (fe, reg0x00[real_qam], p->inversion);
- ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
+ /* yes, this speeds things up: userspace reports lock in about 8 ms
+ instead of 500 to 1200 ms after calling FE_SET_FRONTEND. */
+ mdelay(50);
return 0;
}
-static int ves1820_read_status(struct dvb_frontend* fe, fe_status_t* status)
+
+
+static int ves1820_ioctl (struct dvb_frontend *fe, unsigned int cmd, void *arg)
{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
+ switch (cmd) {
+ case FE_GET_INFO:
+ memcpy (arg, &ves1820_info, sizeof(struct dvb_frontend_info));
+ break;
+
+ case FE_READ_STATUS:
+ {
+ fe_status_t *status = (fe_status_t *) arg;
int sync;
*status = 0;
- sync = ves1820_readreg(state, 0x11);
+ sync = ves1820_readreg (fe, 0x11);
if (sync & 1)
*status |= FE_HAS_SIGNAL;
if (sync & 8)
*status |= FE_HAS_LOCK;
- return 0;
+ break;
}
-static int ves1820_read_ber(struct dvb_frontend* fe, u32* ber)
+ case FE_READ_BER:
{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
-
- u32 _ber = ves1820_readreg(state, 0x14) |
- (ves1820_readreg(state, 0x15) << 8) |
- ((ves1820_readreg(state, 0x16) & 0x0f) << 16);
- *ber = 10 * _ber;
-
- return 0;
+ u32 ber = ves1820_readreg(fe, 0x14) |
+ (ves1820_readreg(fe, 0x15) << 8) |
+ ((ves1820_readreg(fe, 0x16) & 0x0f) << 16);
+ *((u32*) arg) = 10 * ber;
+ break;
}
-
-static int ves1820_read_signal_strength(struct dvb_frontend* fe, u16* strength)
+ case FE_READ_SIGNAL_STRENGTH:
{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
-
- u8 gain = ves1820_readreg(state, 0x17);
- *strength = (gain << 8) | gain;
-
- return 0;
+ u8 gain = ves1820_readreg(fe, 0x17);
+ *((u16*) arg) = (gain << 8) | gain;
+ break;
}
-static int ves1820_read_snr(struct dvb_frontend* fe, u16* snr)
+ case FE_READ_SNR:
{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
-
- u8 quality = ~ves1820_readreg(state, 0x18);
- *snr = (quality << 8) | quality;
-
- return 0;
+ u8 quality = ~ves1820_readreg(fe, 0x18);
+ *((u16*) arg) = (quality << 8) | quality;
+ break;
}
-static int ves1820_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
-{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
-
- *ucblocks = ves1820_readreg(state, 0x13) & 0x7f;
- if (*ucblocks == 0x7f)
- *ucblocks = 0xffffffff;
-
+ case FE_READ_UNCORRECTED_BLOCKS:
+ *((u32*) arg) = ves1820_readreg (fe, 0x13) & 0x7f;
+ if (*((u32*) arg) == 0x7f)
+ *((u32*) arg) = 0xffffffff;
/* reset uncorrected block counter */
- ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
- ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
+ ves1820_writereg (fe, 0x10, ves1820_inittab[0x10] & 0xdf);
+ ves1820_writereg (fe, 0x10, ves1820_inittab[0x10]);
+ break;
- return 0;
-}
+ case FE_SET_FRONTEND:
+ return ves1820_set_parameters (fe, arg);
-static int ves1820_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
+ case FE_GET_FRONTEND:
{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
+ struct dvb_frontend_parameters *p = (struct dvb_frontend_parameters *)arg;
+ u8 reg0 = GET_REG0(fe->data);
int sync;
s8 afc = 0;
- sync = ves1820_readreg(state, 0x11);
- afc = ves1820_readreg(state, 0x19);
+ sync = ves1820_readreg (fe, 0x11);
+ afc = ves1820_readreg(fe, 0x19);
if (verbose) {
/* AFC only valid when carrier has been recovered */
- printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
- "ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->u.qam.symbol_rate * afc) >> 10);
+ printk(sync & 2 ? "DVB: VES1820(%d): AFC (%d) %dHz\n" :
+ "DVB: VES1820(%d): [AFC (%d) %dHz]\n",
+ fe->i2c->adapter->num, afc,
+ -((s32)p->u.qam.symbol_rate * afc) >> 10);
}
- if (!state->config->invert) {
- p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;
- } else {
- p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
- }
-
- p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16;
+ p->inversion = HAS_INVERSION(reg0) ? INVERSION_ON : INVERSION_OFF;
+ p->u.qam.modulation = ((reg0 >> 2) & 7) + QAM_16;
p->u.qam.fec_inner = FEC_NONE;
p->frequency = ((p->frequency + 31250) / 62500) * 62500;
if (sync & 2)
p->frequency -= ((s32)p->u.qam.symbol_rate * afc) >> 10;
+ break;
+ }
+ case FE_SLEEP:
+ ves1820_writereg (fe, 0x1b, 0x02); /* pdown ADC */
+ ves1820_writereg (fe, 0x00, 0x80); /* standby */
+ break;
+
+ case FE_INIT:
+ return ves1820_init (fe);
+
+ default:
+ return -EINVAL;
+ }
return 0;
}
-static int ves1820_sleep(struct dvb_frontend* fe)
-{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
- ves1820_writereg(state, 0x1b, 0x02); /* pdown ADC */
- ves1820_writereg(state, 0x00, 0x80); /* standby */
+static long probe_tuner (struct dvb_i2c_bus *i2c)
+{
+ static const struct i2c_msg msg1 =
+ { .addr = 0x61, .flags = 0, .buf = NULL, .len = 0 };
+ static const struct i2c_msg msg2 =
+ { .addr = 0x62, .flags = 0, .buf = NULL, .len = 0 };
+ int type;
+
+ if (i2c->xfer(i2c, &msg1, 1) == 1) {
+ type = 0;
+ printk ("DVB: VES1820(%d): setup for tuner spXXXX\n", i2c->adapter->num);
+ } else if (i2c->xfer(i2c, &msg2, 1) == 1) {
+ type = 1;
+ printk ("DVB: VES1820(%d): setup for tuner sp5659c\n", i2c->adapter->num);
+ } else {
+ type = -1;
+ }
- return 0;
+ return type;
}
-static int ves1820_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
+
+static u8 read_pwm (struct dvb_i2c_bus *i2c)
{
+ u8 b = 0xff;
+ u8 pwm;
+ struct i2c_msg msg [] = { { .addr = 0x50, .flags = 0, .buf = &b, .len = 1 },
+ { .addr = 0x50, .flags = I2C_M_RD, .buf = &pwm, .len = 1 } };
- fesettings->min_delay_ms = 200;
- fesettings->step_size = 0;
- fesettings->max_drift = 0;
- return 0;
+ if ((i2c->xfer(i2c, msg, 2) != 2) || (pwm == 0xff))
+ pwm = 0x48;
+
+ printk("DVB: VES1820(%d): pwm=0x%02x\n", i2c->adapter->num, pwm);
+
+ return pwm;
}
-static void ves1820_release(struct dvb_frontend* fe)
+
+static long probe_demod_addr (struct dvb_i2c_bus *i2c)
{
- struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
- kfree(state);
+ u8 b [] = { 0x00, 0x1a };
+ u8 id;
+ struct i2c_msg msg [] = { { .addr = 0x08, .flags = 0, .buf = b, .len = 2 },
+ { .addr = 0x08, .flags = I2C_M_RD, .buf = &id, .len = 1 } };
+
+ if (i2c->xfer(i2c, msg, 2) == 2 && (id & 0xf0) == 0x70)
+ return msg[0].addr;
+
+ msg[0].addr = msg[1].addr = 0x09;
+
+ if (i2c->xfer(i2c, msg, 2) == 2 && (id & 0xf0) == 0x70)
+ return msg[0].addr;
+
+ return -1;
}
-static struct dvb_frontend_ops ves1820_ops;
-struct dvb_frontend* ves1820_attach(const struct ves1820_config* config,
- struct i2c_adapter* i2c,
- u8 pwm)
+static int ves1820_attach (struct dvb_i2c_bus *i2c, void **data)
{
- struct ves1820_state* state = NULL;
-
- /* allocate memory for the internal state */
- state = (struct ves1820_state*) kmalloc(sizeof(struct ves1820_state), GFP_KERNEL);
- if (state == NULL)
- goto error;
-
- /* setup the state */
- memcpy(&state->ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));
- state->reg0 = ves1820_inittab[0];
- state->config = config;
- state->i2c = i2c;
- state->pwm = pwm;
-
- /* check if the demod is there */
- if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
- goto error;
-
- if (verbose)
- printk("ves1820: pwm=0x%02x\n", state->pwm);
-
- state->ops.info.symbol_rate_min = (state->config->xin / 2) / 64; /* SACLK/64 == (XIN/2)/64 */
- state->ops.info.symbol_rate_max = (state->config->xin / 2) / 4; /* SACLK/4 */
-
- /* create dvb_frontend */
- state->frontend.ops = &state->ops;
- state->frontend.demodulator_priv = state;
- return &state->frontend;
-
-error:
- if (state) kfree(state);
- return NULL;
+ void *priv = NULL;
+ long demod_addr;
+ long tuner_type;
+
+ if ((demod_addr = probe_demod_addr(i2c)) < 0)
+ return -ENODEV;
+
+ tuner_type = probe_tuner(i2c);
+
+ if ((i2c->adapter->num < MAX_UNITS) && pwm[i2c->adapter->num] != -1) {
+ printk("DVB: VES1820(%d): pwm=0x%02x (user specified)\n",
+ i2c->adapter->num, pwm[i2c->adapter->num]);
+ SET_PWM(priv, pwm[i2c->adapter->num]);
}
+ else
+ SET_PWM(priv, read_pwm(i2c));
+ SET_REG0(priv, ves1820_inittab[0]);
+ SET_TUNER(priv, tuner_type);
+ SET_DEMOD_ADDR(priv, demod_addr);
-static struct dvb_frontend_ops ves1820_ops = {
-
- .info = {
- .name = "VLSI VES1820 DVB-C",
- .type = FE_QAM,
- .frequency_stepsize = 62500,
- .frequency_min = 51000000,
- .frequency_max = 858000000,
- .caps = FE_CAN_QAM_16 |
- FE_CAN_QAM_32 |
- FE_CAN_QAM_64 |
- FE_CAN_QAM_128 |
- FE_CAN_QAM_256 |
- FE_CAN_FEC_AUTO
- },
-
- .release = ves1820_release,
-
- .init = ves1820_init,
- .sleep = ves1820_sleep,
-
- .set_frontend = ves1820_set_parameters,
- .get_frontend = ves1820_get_frontend,
- .get_tune_settings = ves1820_get_tune_settings,
-
- .read_status = ves1820_read_status,
- .read_ber = ves1820_read_ber,
- .read_signal_strength = ves1820_read_signal_strength,
- .read_snr = ves1820_read_snr,
- .read_ucblocks = ves1820_read_ucblocks,
-};
+ return dvb_register_frontend (ves1820_ioctl, i2c, priv, &ves1820_info);
+}
+
+
+static void ves1820_detach (struct dvb_i2c_bus *i2c, void *data)
+{
+ dvb_unregister_frontend (ves1820_ioctl, i2c);
+}
+
+
+static int __init init_ves1820 (void)
+{
+ int i;
+ for (i = 0; i < MAX_UNITS; i++)
+ if (pwm[i] < -1 || pwm[i] > 255)
+ return -EINVAL;
+ return dvb_register_i2c_device (THIS_MODULE,
+ ves1820_attach, ves1820_detach);
+}
+
+
+static void __exit exit_ves1820 (void)
+{
+ dvb_unregister_i2c_device (ves1820_attach);
+}
+
+
+module_init(init_ves1820);
+module_exit(exit_ves1820);
-module_param(verbose, int, 0644);
+MODULE_PARM(pwm, "1-" __MODULE_STRING(MAX_UNITS) "i");
+MODULE_PARM_DESC(pwm, "override PWM value stored in EEPROM (tuner calibration)");
+MODULE_PARM(verbose, "i");
MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
-MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver");
+MODULE_DESCRIPTION("VES1820 DVB-C frontend driver");
MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
MODULE_LICENSE("GPL");
-EXPORT_SYMBOL(ves1820_attach);
git://git.onelab.eu / linux-2.6.git / blobdiff