#include <linux/if_vlan.h>
#include <linux/ctype.h>
#include <linux/crc32.h>
+#include <linux/dma-mapping.h>
#include <asm/system.h>
#include <asm/io.h>
MODULE_AUTHOR("Advanced Micro Devices, Inc.");
MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.3");
MODULE_LICENSE("GPL");
-MODULE_PARM(speed_duplex, "1-" __MODULE_STRING (MAX_UNITS) "i");
+MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
+module_param_array(speed_duplex, int, NULL, 0);
MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
-MODULE_PARM(coalesce, "1-" __MODULE_STRING(MAX_UNITS) "i");
+module_param_array(coalesce, bool, NULL, 0);
MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
-MODULE_PARM(dynamic_ipg, "1-" __MODULE_STRING(MAX_UNITS) "i");
+module_param_array(dynamic_ipg, bool, NULL, 0);
MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
static struct pci_device_id amd8111e_pci_tbl[] = {
short vtag;
#endif
int rx_pkt_limit = dev->quota;
+ unsigned long flags;
do{
/* process receive packets until we use the quota*/
/* Receive descriptor is empty now */
dev->quota -= num_rx_pkt;
*budget -= num_rx_pkt;
+
+ spin_lock_irqsave(&lp->lock, flags);
netif_rx_complete(dev);
- /* enable receive interrupt */
writel(VAL0|RINTEN0, mmio + INTEN0);
writel(VAL2 | RDMD0, mmio + CMD0);
+ spin_unlock_irqrestore(&lp->lock, flags);
return 0;
+
rx_not_empty:
/* Do not call a netif_rx_complete */
dev->quota -= num_rx_pkt;
*budget -= num_rx_pkt;
return 1;
-
-
}
#else
struct net_device * dev = (struct net_device *) dev_id;
struct amd8111e_priv *lp = netdev_priv(dev);
void __iomem *mmio = lp->mmio;
- unsigned int intr0;
+ unsigned int intr0, intren0;
unsigned int handled = 1;
- if(dev == NULL)
+ if(unlikely(dev == NULL))
return IRQ_NONE;
- if (regs) spin_lock (&lp->lock);
+ spin_lock(&lp->lock);
+
/* disabling interrupt */
writel(INTREN, mmio + CMD0);
/* Read interrupt status */
intr0 = readl(mmio + INT0);
+ intren0 = readl(mmio + INTEN0);
/* Process all the INT event until INTR bit is clear. */
writel(intr0, mmio + INT0);
/* Check if Receive Interrupt has occurred. */
-#if CONFIG_AMD8111E_NAPI
+#ifdef CONFIG_AMD8111E_NAPI
if(intr0 & RINT0){
if(netif_rx_schedule_prep(dev)){
/* Disable receive interupts */
/* Schedule a polling routine */
__netif_rx_schedule(dev);
}
- else {
+ else if (intren0 & RINTEN0) {
printk("************Driver bug! \
interrupt while in poll\n");
- /* Fix by disabling interrupts */
- writel(RINT0, mmio + INT0);
+ /* Fix by disable receive interrupts */
+ writel(RINTEN0, mmio + INTEN0);
}
}
#else
err_no_interrupt:
writel( VAL0 | INTREN,mmio + CMD0);
- if (regs) spin_unlock(&lp->lock);
+ spin_unlock(&lp->lock);
return IRQ_RETVAL(handled);
}
if(amd8111e_restart(dev)){
spin_unlock_irq(&lp->lock);
+ if (dev->irq)
+ free_irq(dev->irq, dev);
return -ENOMEM;
}
/* Start ipg timer */
amd8111e crc generator implementation is different from the kernel
ether_crc() function.
*/
-int amd8111e_ether_crc(int len, char* mac_addr)
+static int amd8111e_ether_crc(int len, char* mac_addr)
{
int i,byte;
unsigned char octet;
/*
This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers.
*/
-int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
+static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
{
struct amd8111e_priv *lp = netdev_priv(dev);
int err;
if(!err)
netif_wake_queue(dev);
}
-static int amd8111e_suspend(struct pci_dev *pci_dev, u32 state)
+static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state)
{
struct net_device *dev = pci_get_drvdata(pci_dev);
struct amd8111e_priv *lp = netdev_priv(dev);
if(lp->options & OPTION_WAKE_PHY_ENABLE)
amd8111e_enable_link_change(lp);
- pci_enable_wake(pci_dev, 3, 1);
- pci_enable_wake(pci_dev, 4, 1); /* D3 cold */
+ pci_enable_wake(pci_dev, PCI_D3hot, 1);
+ pci_enable_wake(pci_dev, PCI_D3cold, 1);
}
else{
- pci_enable_wake(pci_dev, 3, 0);
- pci_enable_wake(pci_dev, 4, 0); /* 4 == D3 cold */
+ pci_enable_wake(pci_dev, PCI_D3hot, 0);
+ pci_enable_wake(pci_dev, PCI_D3cold, 0);
}
pci_save_state(pci_dev);
- pci_set_power_state(pci_dev, 3);
+ pci_set_power_state(pci_dev, PCI_D3hot);
return 0;
}
if (!netif_running(dev))
return 0;
- pci_set_power_state(pci_dev, 0);
+ pci_set_power_state(pci_dev, PCI_D0);
pci_restore_state(pci_dev);
- pci_enable_wake(pci_dev, 3, 0);
- pci_enable_wake(pci_dev, 4, 0); /* D3 cold */
+ pci_enable_wake(pci_dev, PCI_D3hot, 0);
+ pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
netif_device_attach(dev);
}
/* Initialize DMA */
- if(!pci_dma_supported(pdev, 0xffffffff)){
+ if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) < 0) {
printk(KERN_ERR "amd8111e: DMA not supported,"
"exiting.\n");
- goto err_free_reg;
- } else
- pdev->dma_mask = 0xffffffff;
+ goto err_free_reg;
+ }
reg_addr = pci_resource_start(pdev, 0);
reg_len = pci_resource_len(pdev, 0);