*
* Copyright (C) 2002 David S. Miller (davem@redhat.com)
* Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
- * Copyright (C) 2006 Broadcom Corporation.
*
* Distribute under GPL.
*/
#define DRV_MODULE_NAME "b44"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "1.00"
-#define DRV_MODULE_RELDATE "Apr 7, 2006"
+#define DRV_MODULE_VERSION "0.97"
+#define DRV_MODULE_RELDATE "Nov 30, 2005"
#define B44_DEF_MSG_ENABLE \
(NETIF_MSG_DRV | \
static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
module_param(b44_debug, int, 0);
MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
-MODULE_VERSION(DRV_MODULE_VERSION);
static struct pci_device_id b44_pci_tbl[] = {
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
return readl(bp->regs + reg);
}
-static inline void bw32(const struct b44 *bp,
+static inline void bw32(const struct b44 *bp,
unsigned long reg, unsigned long val)
{
writel(val, bp->regs + reg);
val |= ((u32) data[4]) << 8;
val |= ((u32) data[5]) << 0;
bw32(bp, B44_CAM_DATA_LO, val);
- val = (CAM_DATA_HI_VALID |
+ val = (CAM_DATA_HI_VALID |
(((u32) data[0]) << 8) |
(((u32) data[1]) << 0));
bw32(bp, B44_CAM_DATA_HI, val);
bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
(index << CAM_CTRL_INDEX_SHIFT)));
- b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
+ b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
}
static inline void __b44_disable_ints(struct b44 *bp)
static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
{
- u32 pause_enab = 0;
+ u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
+ B44_FLAG_RX_PAUSE);
- /* The driver supports only rx pause by default because
- the b44 mac tx pause mechanism generates excessive
- pause frames.
- Use ethtool to turn on b44 tx pause if necessary.
- */
- if ((local & ADVERTISE_PAUSE_CAP) &&
- (local & ADVERTISE_PAUSE_ASYM)){
- if ((remote & LPA_PAUSE_ASYM) &&
- !(remote & LPA_PAUSE_CAP))
- pause_enab |= B44_FLAG_RX_PAUSE;
+ if (local & ADVERTISE_PAUSE_CAP) {
+ if (local & ADVERTISE_PAUSE_ASYM) {
+ if (remote & LPA_PAUSE_CAP)
+ pause_enab |= (B44_FLAG_TX_PAUSE |
+ B44_FLAG_RX_PAUSE);
+ else if (remote & LPA_PAUSE_ASYM)
+ pause_enab |= B44_FLAG_RX_PAUSE;
+ } else {
+ if (remote & LPA_PAUSE_CAP)
+ pause_enab |= (B44_FLAG_TX_PAUSE |
+ B44_FLAG_RX_PAUSE);
+ }
+ } else if (local & ADVERTISE_PAUSE_ASYM) {
+ if ((remote & LPA_PAUSE_CAP) &&
+ (remote & LPA_PAUSE_ASYM))
+ pause_enab |= B44_FLAG_TX_PAUSE;
}
__b44_set_flow_ctrl(bp, pause_enab);
struct ring_info *rp = &bp->tx_buffers[cons];
struct sk_buff *skb = rp->skb;
- BUG_ON(skb == NULL);
+ if (unlikely(skb == NULL))
+ BUG();
pci_unmap_single(bp->pdev,
pci_unmap_addr(rp, mapping),
/* Hardware bug work-around, the chip is unable to do PCI DMA
to/from anything above 1GB :-( */
- if (dma_mapping_error(mapping) ||
- mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
+ if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
/* Sigh... */
- if (!dma_mapping_error(mapping))
- pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
+ pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
dev_kfree_skb_any(skb);
skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
if (skb == NULL)
mapping = pci_map_single(bp->pdev, skb->data,
RX_PKT_BUF_SZ,
PCI_DMA_FROMDEVICE);
- if (dma_mapping_error(mapping) ||
- mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
- if (!dma_mapping_error(mapping))
- pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
+ if (mapping + RX_PKT_BUF_SZ > B44_DMA_MASK) {
+ pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
dev_kfree_skb_any(skb);
return -ENOMEM;
}
}
mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
- if (dma_mapping_error(mapping) || mapping + len > B44_DMA_MASK) {
+ if (mapping + len > B44_DMA_MASK) {
/* Chip can't handle DMA to/from >1GB, use bounce buffer */
- if (!dma_mapping_error(mapping))
- pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
+ pci_unmap_single(bp->pdev, mapping, len, PCI_DMA_TODEVICE);
bounce_skb = __dev_alloc_skb(TX_PKT_BUF_SZ,
GFP_ATOMIC|GFP_DMA);
mapping = pci_map_single(bp->pdev, bounce_skb->data,
len, PCI_DMA_TODEVICE);
- if (dma_mapping_error(mapping) || mapping + len > B44_DMA_MASK) {
- if (!dma_mapping_error(mapping))
- pci_unmap_single(bp->pdev, mapping,
+ if (mapping + len > B44_DMA_MASK) {
+ pci_unmap_single(bp->pdev, mapping,
len, PCI_DMA_TODEVICE);
dev_kfree_skb_any(bounce_skb);
goto err_out;
spin_unlock_irq(&bp->lock);
b44_enable_ints(bp);
-
+
return 0;
}
DMA_TABLE_BYTES,
DMA_BIDIRECTIONAL);
- if (dma_mapping_error(rx_ring_dma) ||
- rx_ring_dma + size > B44_DMA_MASK) {
+ if (rx_ring_dma + size > B44_DMA_MASK) {
kfree(rx_ring);
goto out_err;
}
DMA_TABLE_BYTES,
DMA_TO_DEVICE);
- if (dma_mapping_error(tx_ring_dma) ||
- tx_ring_dma + size > B44_DMA_MASK) {
+ if (tx_ring_dma + size > B44_DMA_MASK) {
kfree(tx_ring);
goto out_err;
}
if (netif_running(dev))
return -EBUSY;
- if (!is_valid_ether_addr(addr->sa_data))
- return -EINVAL;
-
memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
spin_lock_irq(&bp->lock);
bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
bw32(bp, B44_DMARX_PTR, bp->rx_pending);
- bp->rx_prod = bp->rx_pending;
+ bp->rx_prod = bp->rx_pending;
bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
val |= RXCONFIG_ALLMULTI;
else
i = __b44_load_mcast(bp, dev);
-
+
for (; i < 64; i++) {
- __b44_cam_write(bp, zero, i);
+ __b44_cam_write(bp, zero, i);
}
bw32(bp, B44_RXCONFIG, val);
val = br32(bp, B44_CAM_CTRL);
spin_unlock_irq(&bp->lock);
b44_enable_ints(bp);
-
+
return 0;
}
spin_unlock_irq(&bp->lock);
b44_enable_ints(bp);
-
+
return 0;
}
bp->dev->dev_addr[3] = eeprom[80];
bp->dev->dev_addr[4] = eeprom[83];
bp->dev->dev_addr[5] = eeprom[82];
-
- if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
- printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
- return -EINVAL;
- }
-
memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
bp->phy_addr = eeprom[90] & 0x1f;
bp->core_unit = ssb_core_unit(bp);
bp->dma_offset = SB_PCI_DMA;
- /* XXX - really required?
+ /* XXX - really required?
bp->flags |= B44_FLAG_BUGGY_TXPTR;
*/
out:
"aborting.\n");
goto err_out_free_res;
}
-
+
err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
if (err) {
printk(KERN_ERR PFX "No usable DMA configuration, "
pci_save_state(bp->pdev);
- /* Chip reset provides power to the b44 MAC & PCI cores, which
- * is necessary for MAC register access.
- */
- b44_chip_reset(bp);
-
printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
for (i = 0; i < 6; i++)
printk("%2.2x%c", dev->dev_addr[i],
del_timer_sync(&bp->timer);
- spin_lock_irq(&bp->lock);
+ spin_lock_irq(&bp->lock);
b44_halt(bp);
- netif_carrier_off(bp->dev);
+ netif_carrier_off(bp->dev);
netif_device_detach(bp->dev);
b44_free_rings(bp);