/************************************************************************
- * s2io.h: A Linux PCI-X Ethernet driver for S2IO 10GbE Server NIC
- * Copyright 2002 Raghavendra Koushik (raghavendra.koushik@s2io.com)
+ * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
+ * Copyright(c) 2002-2005 Neterion Inc.
* This software may be used and distributed according to the terms of
* the GNU General Public License (GPL), incorporated herein by reference.
#define TBD 0
#define BIT(loc) (0x8000000000000000ULL >> (loc))
#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
+#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
#ifndef BOOL
#define BOOL int
#define SUCCESS 0
#define FAILURE -1
+/* Maximum time to flicker LED when asked to identify NIC using ethtool */
+#define MAX_FLICKER_TIME 60000 /* 60 Secs */
+
/* Maximum outstanding splits to be configured into xena. */
typedef enum xena_max_outstanding_splits {
XENA_ONE_SPLIT_TRANSACTION = 0,
#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
/* OS concerned variables and constants */
-#define WATCH_DOG_TIMEOUT 5*HZ
-#define EFILL 0x1234
-#define ALIGN_SIZE 127
-#define PCIX_COMMAND_REGISTER 0x62
+#define WATCH_DOG_TIMEOUT 15*HZ
+#define EFILL 0x1234
+#define ALIGN_SIZE 127
+#define PCIX_COMMAND_REGISTER 0x62
/*
* Debug related variables.
*/
-#define DEBUG_ON TRUE
-
/* different debug levels. */
#define ERR_DBG 0
#define INIT_DBG 1
#define INTR_DBG 4
/* Global variable that defines the present debug level of the driver. */
-int debug_level = ERR_DBG; /* Default level. */
+static int debug_level = ERR_DBG;
/* DEBUG message print. */
#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
#define L4_CKSUM_OK 0xFFFF
#define S2IO_JUMBO_SIZE 9600
+/* Driver statistics maintained by driver */
+typedef struct {
+ unsigned long long single_ecc_errs;
+ unsigned long long double_ecc_errs;
+ /* LRO statistics */
+ unsigned long long clubbed_frms_cnt;
+ unsigned long long sending_both;
+ unsigned long long outof_sequence_pkts;
+ unsigned long long flush_max_pkts;
+ unsigned long long sum_avg_pkts_aggregated;
+ unsigned long long num_aggregations;
+} swStat_t;
+
/* The statistics block of Xena */
typedef struct stat_block {
-#ifdef __BIG_ENDIAN
-/* Tx MAC statistics counters. */
- u32 tmac_frms;
- u32 tmac_data_octets;
- u64 tmac_drop_frms;
- u32 tmac_mcst_frms;
- u32 tmac_bcst_frms;
- u64 tmac_pause_ctrl_frms;
- u32 tmac_ttl_octets;
- u32 tmac_ucst_frms;
- u32 tmac_nucst_frms;
- u32 tmac_any_err_frms;
- u64 tmac_ttl_less_fb_octets;
- u64 tmac_vld_ip_octets;
- u32 tmac_vld_ip;
- u32 tmac_drop_ip;
- u32 tmac_icmp;
- u32 tmac_rst_tcp;
- u64 tmac_tcp;
- u32 tmac_udp;
- u32 reserved_0;
-
-/* Rx MAC Statistics counters. */
- u32 rmac_vld_frms;
- u32 rmac_data_octets;
- u64 rmac_fcs_err_frms;
- u64 rmac_drop_frms;
- u32 rmac_vld_mcst_frms;
- u32 rmac_vld_bcst_frms;
- u32 rmac_in_rng_len_err_frms;
- u32 rmac_out_rng_len_err_frms;
- u64 rmac_long_frms;
- u64 rmac_pause_ctrl_frms;
- u64 rmac_unsup_ctrl_frms;
- u32 rmac_ttl_octets;
- u32 rmac_accepted_ucst_frms;
- u32 rmac_accepted_nucst_frms;
- u32 rmac_discarded_frms;
- u32 rmac_drop_events;
- u32 reserved_1;
- u64 rmac_ttl_less_fb_octets;
- u64 rmac_ttl_frms;
- u64 reserved_2;
- u32 reserved_3;
- u32 rmac_usized_frms;
- u32 rmac_osized_frms;
- u32 rmac_frag_frms;
- u32 rmac_jabber_frms;
- u32 reserved_4;
- u64 rmac_ttl_64_frms;
- u64 rmac_ttl_65_127_frms;
- u64 reserved_5;
- u64 rmac_ttl_128_255_frms;
- u64 rmac_ttl_256_511_frms;
- u64 reserved_6;
- u64 rmac_ttl_512_1023_frms;
- u64 rmac_ttl_1024_1518_frms;
- u32 reserved_7;
- u32 rmac_ip;
- u64 rmac_ip_octets;
- u32 rmac_hdr_err_ip;
- u32 rmac_drop_ip;
- u32 rmac_icmp;
- u32 reserved_8;
- u64 rmac_tcp;
- u32 rmac_udp;
- u32 rmac_err_drp_udp;
- u64 rmac_xgmii_err_sym;
- u64 rmac_frms_q0;
- u64 rmac_frms_q1;
- u64 rmac_frms_q2;
- u64 rmac_frms_q3;
- u64 rmac_frms_q4;
- u64 rmac_frms_q5;
- u64 rmac_frms_q6;
- u64 rmac_frms_q7;
- u16 rmac_full_q0;
- u16 rmac_full_q1;
- u16 rmac_full_q2;
- u16 rmac_full_q3;
- u16 rmac_full_q4;
- u16 rmac_full_q5;
- u16 rmac_full_q6;
- u16 rmac_full_q7;
- u32 rmac_pause_cnt;
- u32 reserved_9;
- u64 rmac_xgmii_data_err_cnt;
- u64 rmac_xgmii_ctrl_err_cnt;
- u32 rmac_accepted_ip;
- u32 rmac_err_tcp;
-
-/* PCI/PCI-X Read transaction statistics. */
- u32 rd_req_cnt;
- u32 new_rd_req_cnt;
- u32 new_rd_req_rtry_cnt;
- u32 rd_rtry_cnt;
- u32 wr_rtry_rd_ack_cnt;
-
-/* PCI/PCI-X write transaction statistics. */
- u32 wr_req_cnt;
- u32 new_wr_req_cnt;
- u32 new_wr_req_rtry_cnt;
- u32 wr_rtry_cnt;
- u32 wr_disc_cnt;
- u32 rd_rtry_wr_ack_cnt;
-
-/* DMA Transaction statistics. */
- u32 txp_wr_cnt;
- u32 txd_rd_cnt;
- u32 txd_wr_cnt;
- u32 rxd_rd_cnt;
- u32 rxd_wr_cnt;
- u32 txf_rd_cnt;
- u32 rxf_wr_cnt;
-#else
/* Tx MAC statistics counters. */
u32 tmac_data_octets;
u32 tmac_frms;
u32 rxd_rd_cnt;
u32 rxf_wr_cnt;
u32 txf_rd_cnt;
-#endif
+
+/* Tx MAC statistics overflow counters. */
+ u32 tmac_data_octets_oflow;
+ u32 tmac_frms_oflow;
+ u32 tmac_bcst_frms_oflow;
+ u32 tmac_mcst_frms_oflow;
+ u32 tmac_ucst_frms_oflow;
+ u32 tmac_ttl_octets_oflow;
+ u32 tmac_any_err_frms_oflow;
+ u32 tmac_nucst_frms_oflow;
+ u64 tmac_vlan_frms;
+ u32 tmac_drop_ip_oflow;
+ u32 tmac_vld_ip_oflow;
+ u32 tmac_rst_tcp_oflow;
+ u32 tmac_icmp_oflow;
+ u32 tpa_unknown_protocol;
+ u32 tmac_udp_oflow;
+ u32 reserved_10;
+ u32 tpa_parse_failure;
+
+/* Rx MAC Statistics overflow counters. */
+ u32 rmac_data_octets_oflow;
+ u32 rmac_vld_frms_oflow;
+ u32 rmac_vld_bcst_frms_oflow;
+ u32 rmac_vld_mcst_frms_oflow;
+ u32 rmac_accepted_ucst_frms_oflow;
+ u32 rmac_ttl_octets_oflow;
+ u32 rmac_discarded_frms_oflow;
+ u32 rmac_accepted_nucst_frms_oflow;
+ u32 rmac_usized_frms_oflow;
+ u32 rmac_drop_events_oflow;
+ u32 rmac_frag_frms_oflow;
+ u32 rmac_osized_frms_oflow;
+ u32 rmac_ip_oflow;
+ u32 rmac_jabber_frms_oflow;
+ u32 rmac_icmp_oflow;
+ u32 rmac_drop_ip_oflow;
+ u32 rmac_err_drp_udp_oflow;
+ u32 rmac_udp_oflow;
+ u32 reserved_11;
+ u32 rmac_pause_cnt_oflow;
+ u64 rmac_ttl_1519_4095_frms;
+ u64 rmac_ttl_4096_8191_frms;
+ u64 rmac_ttl_8192_max_frms;
+ u64 rmac_ttl_gt_max_frms;
+ u64 rmac_osized_alt_frms;
+ u64 rmac_jabber_alt_frms;
+ u64 rmac_gt_max_alt_frms;
+ u64 rmac_vlan_frms;
+ u32 rmac_len_discard;
+ u32 rmac_fcs_discard;
+ u32 rmac_pf_discard;
+ u32 rmac_da_discard;
+ u32 rmac_red_discard;
+ u32 rmac_rts_discard;
+ u32 reserved_12;
+ u32 rmac_ingm_full_discard;
+ u32 reserved_13;
+ u32 rmac_accepted_ip_oflow;
+ u32 reserved_14;
+ u32 link_fault_cnt;
+ swStat_t sw_stat;
} StatInfo_t;
-/* Structures representing different init time configuration
+/*
+ * Structures representing different init time configuration
* parameters of the NIC.
*/
+#define MAX_TX_FIFOS 8
+#define MAX_RX_RINGS 8
+
+/* FIFO mappings for all possible number of fifos configured */
+static int fifo_map[][MAX_TX_FIFOS] = {
+ {0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 1, 1, 1, 1},
+ {0, 0, 0, 1, 1, 1, 2, 2},
+ {0, 0, 1, 1, 2, 2, 3, 3},
+ {0, 0, 1, 1, 2, 2, 3, 4},
+ {0, 0, 1, 1, 2, 3, 4, 5},
+ {0, 0, 1, 2, 3, 4, 5, 6},
+ {0, 1, 2, 3, 4, 5, 6, 7},
+};
+
/* Maintains Per FIFO related information. */
typedef struct tx_fifo_config {
#define MAX_AVAILABLE_TXDS 8192
- u32 FifoLen; /* specifies len of FIFO upto 8192, ie no of TxDLs */
+ u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
/* Priority definition */
#define TX_FIFO_PRI_0 0 /*Highest */
#define TX_FIFO_PRI_1 1
#define TX_FIFO_PRI_5 5
#define TX_FIFO_PRI_6 6
#define TX_FIFO_PRI_7 7 /*lowest */
- u8 FifoPriority; /* specifies pointer level for FIFO */
+ u8 fifo_priority; /* specifies pointer level for FIFO */
/* user should not set twos fifos with same pri */
- u8 fNoSnoop;
+ u8 f_no_snoop;
#define NO_SNOOP_TXD 0x01
#define NO_SNOOP_TXD_BUFFER 0x02
} tx_fifo_config_t;
/* Maintains per Ring related information */
typedef struct rx_ring_config {
- u32 NumRxd; /*No of RxDs per Rx Ring */
+ u32 num_rxd; /*No of RxDs per Rx Ring */
#define RX_RING_PRI_0 0 /* highest */
#define RX_RING_PRI_1 1
#define RX_RING_PRI_2 2
#define RX_RING_PRI_6 6
#define RX_RING_PRI_7 7 /* lowest */
- u8 RingPriority; /*Specifies service priority of ring */
+ u8 ring_priority; /*Specifies service priority of ring */
/* OSM should not set any two rings with same priority */
- u8 RingOrg; /*Organization of ring */
-#define RING_ORG_BUFF1 0x01
-#define RX_RING_ORG_BUFF3 0x03
-#define RX_RING_ORG_BUFF5 0x05
-
-/* In case of 3 buffer recv. mode, size of three buffers is expected as.. */
-#define BUFF_SZ_1 22 /* ethernet header */
-#define BUFF_SZ_2 (64+64) /* max. IP+TCP header size */
-#define BUFF_SZ_3 (1500-20-20) /* TCP payload */
-#define BUFF_SZ_3_JUMBO (9600-20-20) /* Jumbo TCP payload */
-
- u32 RxdThresh; /*No of used Rxds NIC can store before transfer to host */
-#define DEFAULT_RXD_THRESHOLD 0x1 /* TODO */
- u8 fNoSnoop;
+ u8 ring_org; /*Organization of ring */
+#define RING_ORG_BUFF1 0x01
+#define RX_RING_ORG_BUFF3 0x03
+#define RX_RING_ORG_BUFF5 0x05
+
+ u8 f_no_snoop;
#define NO_SNOOP_RXD 0x01
#define NO_SNOOP_RXD_BUFFER 0x02
- u32 RxD_BackOff_Interval;
-#define RXD_BACKOFF_INTERVAL_DEF 0x0
-#define RXD_BACKOFF_INTERVAL_MIN 0x0
-#define RXD_BACKOFF_INTERVAL_MAX 0x0
} rx_ring_config_t;
-/* This structure provides contains values of the tunable parameters
- * of the H/W
+/* This structure provides contains values of the tunable parameters
+ * of the H/W
*/
struct config_param {
-
/* Tx Side */
- u32 TxFIFONum; /*Number of Tx FIFOs */
-#define MAX_TX_FIFOS 8
+ u32 tx_fifo_num; /*Number of Tx FIFOs */
- tx_fifo_config_t TxCfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
- u32 MaxTxDs; /*Max no. of Tx buffer descriptor per TxDL */
- BOOL TxVLANEnable; /*TRUE: Insert VLAN ID, FALSE: Don't insert */
-#define TX_REQ_TIMEOUT_DEFAULT 0x0
-#define TX_REQ_TIMEOUT_MIN 0x0
-#define TX_REQ_TIMEOUT_MAX 0x0
- u32 TxReqTimeOut;
- BOOL TxFlow; /*Tx flow control enable */
- BOOL RxFlow;
- BOOL OverrideTxServiceState; /* TRUE: Overide, FALSE: Do not override
- Use the new priority information
- of service state. It is not recommended
- to change but OSM can opt to do so */
-#define MAX_SERVICE_STATES 36
- u8 TxServiceState[MAX_SERVICE_STATES];
- /* Array element represent 'priority'
- * and array index represents
- * 'Service state' e.g.
- * TxServiceState[3]=7; it means
- * Service state 3 is associated
- * with priority 7 of a Tx FIFO */
- u64 TxIntrType; /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
+ u8 fifo_mapping[MAX_TX_FIFOS];
+ tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
+ u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
+ u64 tx_intr_type;
+ /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
/* Rx Side */
- u32 RxRingNum; /*Number of receive rings */
-#define MAX_RX_RINGS 8
+ u32 rx_ring_num; /*Number of receive rings */
#define MAX_RX_BLOCKS_PER_RING 150
- rx_ring_config_t RxCfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
- BOOL RxVLANEnable; /*TRUE: Strip off VLAN tag from the frame,
- FALSE: Don't strip off VLAN tag */
+ rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
+ u8 bimodal; /*Flag for setting bimodal interrupts*/
#define HEADER_ETHERNET_II_802_3_SIZE 14
#define HEADER_802_2_SIZE 3
#define MAX_PYLD_JUMBO 9600
#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
- u32 MTU; /*Maximum Payload */
- BOOL JumboEnable; /*Enable Jumbo frames recv/send */
- BOOL OverrideRxServiceState; /* TRUE: Overide, FALSE: Do not override
- Use the new priority information
- of service state. It is not recommended
- to change but OSM can opt to do so */
-#define MAX_SERVICE_STATES 36
- u8 RxServiceState[MAX_SERVICE_STATES];
- /* Array element represent 'priority'
- * and array index represents
- * 'Service state'e.g.
- * RxServiceState[3]=7; it means
- * Service state 3 is associated
- * with priority 7 of a Rx FIFO */
- BOOL StatAutoRefresh; /* When true, StatRefreshTime have valid value */
- u32 StatRefreshTime; /*Time for refreshing statistics */
-#define STAT_TRSF_PER_1_SECOND 0x208D5
+ u16 bus_speed;
};
/* Structure representing MAC Addrs */
} macaddr_t;
/* Structure that represent every FIFO element in the BAR1
- * Address location.
+ * Address location.
*/
typedef struct _TxFIFO_element {
u64 TxDL_Pointer;
#define TXD_GATHER_CODE_LAST BIT(23)
#define TXD_TCP_LSO_EN BIT(30)
#define TXD_UDP_COF_EN BIT(31)
+#define TXD_UFO_EN BIT(31) | BIT(30)
#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
+#define TXD_UFO_MSS(val) vBIT(val,34,14)
#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
u64 Control_2;
u64 Host_Control; /* reserved for host */
} TxD_t;
-/* Rx descriptor structure */
+/* Structure to hold the phy and virt addr of every TxDL. */
+typedef struct list_info_hold {
+ dma_addr_t list_phy_addr;
+ void *list_virt_addr;
+} list_info_hold_t;
+
+/* Rx descriptor structure for 1 buffer mode */
typedef struct _RxD_t {
u64 Host_Control; /* reserved for host */
u64 Control_1;
#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
#define RXD_FRAME_PROTO_IPV4 BIT(27)
#define RXD_FRAME_PROTO_IPV6 BIT(28)
+#define RXD_FRAME_IP_FRAG BIT(29)
#define RXD_FRAME_PROTO_TCP BIT(30)
#define RXD_FRAME_PROTO_UDP BIT(31)
#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
u64 Control_2;
-#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
-#define SET_BUFFER0_SIZE(val) vBIT(val,0,16)
+#define THE_RXD_MARK 0x3
+#define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2)
+#define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62)
+
#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
#define SET_VLAN_TAG(val) vBIT(val,48,16)
#define SET_NUM_TAG(val) vBIT(val,16,32)
-#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
-/*
-#define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31))
-#define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47))
-*/
- u64 Buffer0_ptr;
+
} RxD_t;
+/* Rx descriptor structure for 1 buffer mode */
+typedef struct _RxD1_t {
+ struct _RxD_t h;
+
+#define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14)
+#define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14)
+#define RXD_GET_BUFFER0_SIZE_1(_Control_2) \
+ (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48)
+ u64 Buffer0_ptr;
+} RxD1_t;
+/* Rx descriptor structure for 3 or 2 buffer mode */
+
+typedef struct _RxD3_t {
+ struct _RxD_t h;
+
+#define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14)
+#define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16)
+#define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16)
+#define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8)
+#define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16)
+#define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16)
+#define RXD_GET_BUFFER0_SIZE_3(Control_2) \
+ (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48)
+#define RXD_GET_BUFFER1_SIZE_3(Control_2) \
+ (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32)
+#define RXD_GET_BUFFER2_SIZE_3(Control_2) \
+ (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16)
+#define BUF0_LEN 40
+#define BUF1_LEN 1
+
+ u64 Buffer0_ptr;
+ u64 Buffer1_ptr;
+ u64 Buffer2_ptr;
+} RxD3_t;
-/* Structure that represents the Rx descriptor block which contains
+/* Structure that represents the Rx descriptor block which contains
* 128 Rx descriptors.
*/
typedef struct _RxD_block {
-#define MAX_RXDS_PER_BLOCK 127
- RxD_t rxd[MAX_RXDS_PER_BLOCK];
+#define MAX_RXDS_PER_BLOCK_1 127
+ RxD1_t rxd[MAX_RXDS_PER_BLOCK_1];
u64 reserved_0;
#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
- u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */
- u64 reserved_2_pNext_RxD_block; /*@ Logical ptr to next */
- u64 pNext_RxD_Blk_physical; /* Buff0_ptr.
- In a 32 bit arch the upper 32 bits
- should be 0 */
+ u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
+ * Rxd in this blk */
+ u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
+ u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
+ * the upper 32 bits should
+ * be 0 */
} RxD_block_t;
+#define SIZE_OF_BLOCK 4096
+
+#define RXD_MODE_1 0
+#define RXD_MODE_3A 1
+#define RXD_MODE_3B 2
+
+/* Structure to hold virtual addresses of Buf0 and Buf1 in
+ * 2buf mode. */
+typedef struct bufAdd {
+ void *ba_0_org;
+ void *ba_1_org;
+ void *ba_0;
+ void *ba_1;
+} buffAdd_t;
+
/* Structure which stores all the MAC control parameters */
-/* This structure stores the offset of the RxD in the ring
- * from which the Rx Interrupt processor can start picking
+/* This structure stores the offset of the RxD in the ring
+ * from which the Rx Interrupt processor can start picking
* up the RxDs for processing.
*/
typedef struct _rx_curr_get_info_t {
typedef rx_curr_get_info_t rx_curr_put_info_t;
/* This structure stores the offset of the TxDl in the FIFO
- * from which the Tx Interrupt processor can start picking
+ * from which the Tx Interrupt processor can start picking
* up the TxDLs for send complete interrupt processing.
*/
typedef struct {
typedef tx_curr_get_info_t tx_curr_put_info_t;
-/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
- * is maintained in this structure.
- */
-typedef struct mac_info {
-/* rx side stuff */
- u32 rxd_ring_mem_sz;
- RxD_t *RxRing[MAX_RX_RINGS]; /* Logical Rx ring pointers */
- dma_addr_t RxRing_Phy[MAX_RX_RINGS];
- /* Put pointer info which indictes which RxD has to be replenished
+typedef struct rxd_info {
+ void *virt_addr;
+ dma_addr_t dma_addr;
+}rxd_info_t;
+
+/* Structure that holds the Phy and virt addresses of the Blocks */
+typedef struct rx_block_info {
+ void *block_virt_addr;
+ dma_addr_t block_dma_addr;
+ rxd_info_t *rxds;
+} rx_block_info_t;
+
+/* pre declaration of the nic structure */
+typedef struct s2io_nic nic_t;
+
+/* Ring specific structure */
+typedef struct ring_info {
+ /* The ring number */
+ int ring_no;
+
+ /*
+ * Place holders for the virtual and physical addresses of
+ * all the Rx Blocks
+ */
+ rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
+ int block_count;
+ int pkt_cnt;
+
+ /*
+ * Put pointer info which indictes which RxD has to be replenished
* with a new buffer.
*/
- rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS];
+ rx_curr_put_info_t rx_curr_put_info;
- /* Get pointer info which indictes which is the last RxD that was
+ /*
+ * Get pointer info which indictes which is the last RxD that was
* processed by the driver.
*/
- rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
+ rx_curr_get_info_t rx_curr_get_info;
- u16 rmac_pause_time;
+#ifndef CONFIG_S2IO_NAPI
+ /* Index to the absolute position of the put pointer of Rx ring */
+ int put_pos;
+#endif
+
+ /* Buffer Address store. */
+ buffAdd_t **ba;
+ nic_t *nic;
+} ring_info_t;
+
+/* Fifo specific structure */
+typedef struct fifo_info {
+ /* FIFO number */
+ int fifo_no;
- /* this will be used in receive function, this decides which ring would
- be processed first. eg: ring with priority value 0 (highest) should
- be processed first.
- first 3 LSB bits represent ring number which should be processed
- first, similarly next 3 bits represent next ring to be processed.
- eg: value of _rx_ring_pri_map = 0x0000 003A means
- ring #2 would be processed first and #7 would be processed next
+ /* Maximum TxDs per TxDL */
+ int max_txds;
+
+ /* Place holder of all the TX List's Phy and Virt addresses. */
+ list_info_hold_t *list_info;
+
+ /*
+ * Current offset within the tx FIFO where driver would write
+ * new Tx frame
*/
- u32 _rx_ring_pri_map;
+ tx_curr_put_info_t tx_curr_put_info;
-/* tx side stuff */
- void *txd_list_mem; /* orignal pointer to allocated mem */
- dma_addr_t txd_list_mem_phy;
- u32 txd_list_mem_sz;
+ /*
+ * Current offset within tx FIFO from where the driver would start freeing
+ * the buffers
+ */
+ tx_curr_get_info_t tx_curr_get_info;
+
+ nic_t *nic;
+}fifo_info_t;
+/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
+ * is maintained in this structure.
+ */
+typedef struct mac_info {
+/* tx side stuff */
/* logical pointer of start of each Tx FIFO */
- TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS];
+ TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
- /* logical pointer of start of TxDL which corresponds to each Tx FIFO */
- TxD_t *txdl_start[MAX_TX_FIFOS];
+ /* Fifo specific structure */
+ fifo_info_t fifos[MAX_TX_FIFOS];
- /* Same as txdl_start but phy addr */
- dma_addr_t txdl_start_phy[MAX_TX_FIFOS];
+ /* Save virtual address of TxD page with zero DMA addr(if any) */
+ void *zerodma_virt_addr;
-/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
- tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
- tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
+/* rx side stuff */
+ /* Ring specific structure */
+ ring_info_t rings[MAX_RX_RINGS];
- u16 txdl_len; /* length of a TxDL, same for all */
+ u16 rmac_pause_time;
+ u16 mc_pause_threshold_q0q3;
+ u16 mc_pause_threshold_q4q7;
void *stats_mem; /* orignal pointer to allocated mem */
dma_addr_t stats_mem_phy; /* Physical address of the stat block */
u32 stats_mem_sz;
- StatInfo_t *StatsInfo; /* Logical address of the stat block */
+ StatInfo_t *stats_info; /* Logical address of the stat block */
} mac_info_t;
/* structure representing the user defined MAC addresses */
int usage_cnt;
} usr_addr_t;
-/* Structure that holds the Phy and virt addresses of the Blocks */
-typedef struct rx_block_info {
- RxD_t *block_virt_addr;
- dma_addr_t block_dma_addr;
-} rx_block_info_t;
+/* Default Tunable parameters of the NIC. */
+#define DEFAULT_FIFO_LEN 4096
+#define SMALL_BLK_CNT 30
+#define LARGE_BLK_CNT 100
+
+/*
+ * Structure to keep track of the MSI-X vectors and the corresponding
+ * argument registered against each vector
+ */
+#define MAX_REQUESTED_MSI_X 17
+struct s2io_msix_entry
+{
+ u16 vector;
+ u16 entry;
+ void *arg;
+
+ u8 type;
+#define MSIX_FIFO_TYPE 1
+#define MSIX_RING_TYPE 2
+
+ u8 in_use;
+#define MSIX_REGISTERED_SUCCESS 0xAA
+};
+
+struct msix_info_st {
+ u64 addr;
+ u64 data;
+};
+
+/* Data structure to represent a LRO session */
+typedef struct lro {
+ struct sk_buff *parent;
+ u8 *l2h;
+ struct iphdr *iph;
+ struct tcphdr *tcph;
+ u32 tcp_next_seq;
+ u32 tcp_ack;
+ int total_len;
+ int frags_len;
+ int sg_num;
+ int in_use;
+ u16 window;
+ u32 cur_tsval;
+ u32 cur_tsecr;
+ u8 saw_ts;
+}lro_t;
/* Structure representing one instance of the NIC */
-typedef struct s2io_nic {
+struct s2io_nic {
+ int rxd_mode;
+#ifdef CONFIG_S2IO_NAPI
+ /*
+ * Count of packets to be processed in a given iteration, it will be indicated
+ * by the quota field of the device structure when NAPI is enabled.
+ */
+ int pkts_to_process;
+#endif
+ struct net_device *dev;
+ mac_info_t mac_control;
+ struct config_param config;
+ struct pci_dev *pdev;
+ void __iomem *bar0;
+ void __iomem *bar1;
#define MAX_MAC_SUPPORTED 16
#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
- macaddr_t defMacAddr[MAX_MAC_SUPPORTED];
- macaddr_t preMacAddr[MAX_MAC_SUPPORTED];
+ macaddr_t def_mac_addr[MAX_MAC_SUPPORTED];
+ macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
struct net_device_stats stats;
- caddr_t bar0;
- caddr_t bar1;
- struct config_param config;
- mac_info_t mac_control;
int high_dma_flag;
int device_close_flag;
int device_enabled_once;
- char name[32];
+ char name[50];
struct tasklet_struct task;
- atomic_t tasklet_status;
- struct timer_list timer;
- struct net_device *dev;
- struct pci_dev *pdev;
+ volatile unsigned long tasklet_status;
+
+ /* Timer that handles I/O errors/exceptions */
+ struct timer_list alarm_timer;
- u16 vendor_id;
- u16 device_id;
- u16 ccmd;
- u32 cbar0_1;
- u32 cbar0_2;
- u32 cbar1_1;
- u32 cbar1_2;
- u32 cirq;
- u8 cache_line;
- u32 rom_expansion;
- u16 pcix_cmd;
+ /* Space to back up the PCI config space */
u32 config_space[256 / sizeof(u32)];
- u32 irq;
+
atomic_t rx_bufs_left[MAX_RX_RINGS];
- spinlock_t isr_lock;
spinlock_t tx_lock;
+#ifndef CONFIG_S2IO_NAPI
+ spinlock_t put_lock;
+#endif
#define PROMISC 1
#define ALL_MULTI 2
u16 tx_err_count;
u16 rx_err_count;
-#if DEBUG_ON
- u64 rxpkt_bytes;
- u64 txpkt_bytes;
- int int_cnt;
- int rxint_cnt;
- int txint_cnt;
- u64 rxpkt_cnt;
-#endif
-
- /* Place holders for the virtual and physical addresses of
- * all the Rx Blocks
- */
- struct rx_block_info
- rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
- int block_count[MAX_RX_RINGS];
- int pkt_cnt[MAX_RX_RINGS];
-
/* Id timer, used to blink NIC to physically identify NIC. */
struct timer_list id_timer;
/* Restart timer, used to restart NIC if the device is stuck and
- * a schedule task that will set the correct Link state once the
+ * a schedule task that will set the correct Link state once the
* NIC's PHY has stabilized after a state change.
*/
-#ifdef INIT_TQUEUE
- struct tq_struct rst_timer_task;
- struct tq_struct set_link_task;
-#else
struct work_struct rst_timer_task;
struct work_struct set_link_task;
-#endif
- /* Flag that can be used to turn on or turn off the Rx checksum
+ /* Flag that can be used to turn on or turn off the Rx checksum
* offload feature.
*/
int rx_csum;
- /* after blink, the adapter must be restored with original
+ /* after blink, the adapter must be restored with original
* values.
*/
u64 adapt_ctrl_org;
u16 last_link_state;
#define LINK_DOWN 1
#define LINK_UP 2
-} nic_t;
+
+ int task_flag;
+#define CARD_DOWN 1
+#define CARD_UP 2
+ atomic_t card_state;
+ volatile unsigned long link_state;
+ struct vlan_group *vlgrp;
+#define MSIX_FLG 0xA5
+ struct msix_entry *entries;
+ struct s2io_msix_entry *s2io_entries;
+ char desc1[35];
+ char desc2[35];
+
+ struct msix_info_st msix_info[0x3f];
+
+#define XFRAME_I_DEVICE 1
+#define XFRAME_II_DEVICE 2
+ u8 device_type;
+
+#define MAX_LRO_SESSIONS 32
+ lro_t lro0_n[MAX_LRO_SESSIONS];
+ unsigned long clubbed_frms_cnt;
+ unsigned long sending_both;
+ u8 lro;
+ u16 lro_max_aggr_per_sess;
+
+#define INTA 0
+#define MSI 1
+#define MSI_X 2
+ u8 intr_type;
+
+ spinlock_t rx_lock;
+ atomic_t isr_cnt;
+ u64 *ufo_in_band_v;
+};
#define RESET_ERROR 1;
#define CMD_ERROR 2;
-/* Default Tunable parameters of the NIC. */
-#define DEFAULT_FIFO_LEN 4096
-#define SMALL_RXD_CNT 40 * (MAX_RXDS_PER_BLOCK+1)
-#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
-
/* OS related system calls */
#ifndef readq
-static inline u64 readq(void *addr)
+static inline u64 readq(void __iomem *addr)
{
u64 ret = 0;
ret = readl(addr + 4);
#endif
#ifndef writeq
-static inline void writeq(u64 val, void *addr)
+static inline void writeq(u64 val, void __iomem *addr)
{
writel((u32) (val), addr);
writel((u32) (val >> 32), (addr + 4));
}
+
+/* In 32 bit modes, some registers have to be written in a
+ * particular order to expect correct hardware operation. The
+ * macro SPECIAL_REG_WRITE is used to perform such ordered
+ * writes. Defines UF (Upper First) and LF (Lower First) will
+ * be used to specify the required write order.
+ */
+#define UF 1
+#define LF 2
+static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
+{
+ if (order == LF) {
+ writel((u32) (val), addr);
+ writel((u32) (val >> 32), (addr + 4));
+ } else {
+ writel((u32) (val >> 32), (addr + 4));
+ writel((u32) (val), addr);
+ }
+}
+#else
+#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
#endif
/* Interrupt related values of Xena */
/* DMA level Inressupts */
#define TXDMA_PFC_INT_M BIT(0)
- /* PFC block interrupts */
+#define TXDMA_PCC_INT_M BIT(2)
+
+/* PFC block interrupts */
#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
+/* PCC block interrupts. */
+#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
+ PCC_FB_ECC Error. */
+
+#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
/*
* Prototype declaration.
*/
static int __devinit s2io_init_nic(struct pci_dev *pdev,
const struct pci_device_id *pre);
static void __devexit s2io_rem_nic(struct pci_dev *pdev);
-static int initSharedMem(struct s2io_nic *sp);
-static void freeSharedMem(struct s2io_nic *sp);
-static int initNic(struct s2io_nic *nic);
-#ifndef CONFIG_S2IO_NAPI
-static void rxIntrHandler(struct s2io_nic *sp);
-#endif
-static void txIntrHandler(struct s2io_nic *sp);
-static void alarmIntrHandler(struct s2io_nic *sp);
+static int init_shared_mem(struct s2io_nic *sp);
+static void free_shared_mem(struct s2io_nic *sp);
+static int init_nic(struct s2io_nic *nic);
+static void rx_intr_handler(ring_info_t *ring_data);
+static void tx_intr_handler(fifo_info_t *fifo_data);
+static void alarm_intr_handler(struct s2io_nic *sp);
static int s2io_starter(void);
-void s2io_closer(void);
static void s2io_tx_watchdog(struct net_device *dev);
static void s2io_tasklet(unsigned long dev_addr);
static void s2io_set_multicast(struct net_device *dev);
-static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
-void s2io_link(nic_t * sp, int link);
-void s2io_reset(nic_t * sp);
-#ifdef CONFIG_S2IO_NAPI
+static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
+static void s2io_link(nic_t * sp, int link);
+#if defined(CONFIG_S2IO_NAPI)
static int s2io_poll(struct net_device *dev, int *budget);
#endif
static void s2io_init_pci(nic_t * sp);
-int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
+static int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
+static void s2io_alarm_handle(unsigned long data);
+static int s2io_enable_msi(nic_t *nic);
+static irqreturn_t s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs);
+static irqreturn_t
+s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs);
+static irqreturn_t
+s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs);
static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
-static int verify_xena_quiescence(u64 val64, int flag);
+static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
static struct ethtool_ops netdev_ethtool_ops;
-
+static void s2io_set_link(unsigned long data);
+static int s2io_set_swapper(nic_t * sp);
+static void s2io_card_down(nic_t *nic);
+static int s2io_card_up(nic_t *nic);
+static int get_xena_rev_id(struct pci_dev *pdev);
+static void restore_xmsi_data(nic_t *nic);
+
+static int s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro, RxD_t *rxdp, nic_t *sp);
+static void clear_lro_session(lro_t *lro);
+static void queue_rx_frame(struct sk_buff *skb);
+static void update_L3L4_header(nic_t *sp, lro_t *lro);
+static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb, u32 tcp_len);
#endif /* _S2IO_H */
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