lp->asBitValid = TRUE;
lp->timeout = -1;
lp->gendev = gendev;
- lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
+ lp->lock = SPIN_LOCK_UNLOCKED;
init_timer(&lp->timer);
de4x5_parse_params(dev);
** Re-initialize the DE4X5...
*/
status = de4x5_init(dev);
- lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
+ lp->lock = SPIN_LOCK_UNLOCKED;
lp->state = OPEN;
de4x5_dbg_open(dev);
return -ENODEV;
/* Ok, the device seems to be for us. */
- if (!(dev = alloc_etherdev (sizeof (struct de4x5_private))))
- return -ENOMEM;
+ if (pci_enable_device (pdev))
+ return -ENODEV;
+
+ if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
+ error = -ENOMEM;
+ goto disable_dev;
+ }
lp = netdev_priv(dev);
lp->bus = PCI;
release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
free_dev:
free_netdev (dev);
+ disable_dev:
+ pci_disable_device (pdev);
return error;
}
unregister_netdev (dev);
free_netdev (dev);
release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
+ pci_disable_device (pdev);
}
static struct pci_device_id de4x5_pci_tbl[] = {
if (lp->state == INITIALISED) {
lp->ibn = 1;
lp->active = *p++;
- lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
- lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
+ lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
+ lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
lp->ibn = 3;
lp->active = *p++;
if (MOTO_SROM_BUG) lp->active = 0;
- lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
- lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
+ lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
+ lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
{
struct de4x5_private *lp = netdev_priv(dev);
- struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
+ struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
u_long iobase = dev->base_addr;
int i, j, status = 0;
s32 omr;