*/
+#include <linux/pci.h>
#include "tulip.h"
#include <linux/init.h>
#include <asm/unaligned.h>
*/
{ 0x1e00, 0x0000, 0x000b, 0x8f01, 0x0103, 0x0300, 0x0821, 0x000, 0x0001, 0x0000, 0x01e1 }
},
- {0, 0, 0, 0, {}}};
+ {"Cobalt Microserver", 0, 0x10, 0xE0, {0x1e00, /* 0 == controller #, 1e == offset */
+ 0x0000, /* 0 == high offset, 0 == gap */
+ 0x0800, /* Default Autoselect */
+ 0x8001, /* 1 leaf, extended type, bogus len */
+ 0x0003, /* Type 3 (MII), PHY #0 */
+ 0x0400, /* 0 init instr, 4 reset instr */
+ 0x0801, /* Set control mode, GP0 output */
+ 0x0000, /* Drive GP0 Low (RST is active low) */
+ 0x0800, /* control mode, GP0 input (undriven) */
+ 0x0000, /* clear control mode */
+ 0x7800, /* 100TX FDX + HDX, 10bT FDX + HDX */
+ 0x01e0, /* Advertise all above */
+ 0x5000, /* FDX all above */
+ 0x1800, /* Set fast TTM in 100bt modes */
+ 0x0000, /* PHY cannot be unplugged */
+ }},
+ {NULL}};
static const char *block_name[] __devinitdata = {
unsigned char *ee_data = tp->eeprom;
int i;
- tp->mtable = 0;
+ tp->mtable = NULL;
/* Detect an old-style (SA only) EEPROM layout:
memcmp(eedata, eedata+16, 8). */
for (i = 0; i < 8; i ++)
/* Delay between EEPROM clock transitions.
Even at 33Mhz current PCI implementations don't overrun the EEPROM clock.
We add a bus turn-around to insure that this remains true. */
-#define eeprom_delay() inl(ee_addr)
+#define eeprom_delay() ioread32(ee_addr)
/* The EEPROM commands include the alway-set leading bit. */
#define EE_READ_CMD (6)
int i;
unsigned retval = 0;
struct tulip_private *tp = dev->priv;
- long ee_addr = tp->base_addr + CSR9;
+ void __iomem *ee_addr = tp->base_addr + CSR9;
int read_cmd = location | (EE_READ_CMD << addr_len);
- outl(EE_ENB & ~EE_CS, ee_addr);
- outl(EE_ENB, ee_addr);
+ iowrite32(EE_ENB & ~EE_CS, ee_addr);
+ iowrite32(EE_ENB, ee_addr);
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
- outl(EE_ENB | dataval, ee_addr);
+ iowrite32(EE_ENB | dataval, ee_addr);
eeprom_delay();
- outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
+ iowrite32(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
- retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
+ retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
}
- outl(EE_ENB, ee_addr);
+ iowrite32(EE_ENB, ee_addr);
eeprom_delay();
for (i = 16; i > 0; i--) {
- outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
+ iowrite32(EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
- retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
- outl(EE_ENB, ee_addr);
+ retval = (retval << 1) | ((ioread32(ee_addr) & EE_DATA_READ) ? 1 : 0);
+ iowrite32(EE_ENB, ee_addr);
eeprom_delay();
}
/* Terminate the EEPROM access. */
- outl(EE_ENB & ~EE_CS, ee_addr);
+ iowrite32(EE_ENB & ~EE_CS, ee_addr);
return (tp->flags & HAS_SWAPPED_SEEPROM) ? swab16(retval) : retval;
}