int n_ports; /* 1, 2 or 4 ports */
u8 irq;
- u8 *plx; /* PLX PCI9060 virtual base address */
+ u8 __iomem *plx; /* PLX PCI9060 virtual base address */
struct pci_dev *pdev; /* for pdev->slot_name */
int rx_in;
struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
#endif
stats->rx_packets++;
stats->rx_bytes += skb->len;
- skb->mac.raw = skb->data;
- skb->dev = dev;
dev->last_rx = jiffies;
skb->protocol = hdlc_type_trans(skb, dev);
netif_rx(skb);
static int wanxl_open(struct net_device *dev)
{
port_t *port = dev_to_port(dev);
- u8 *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
+ u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
unsigned long timeout;
int i;
timeout = jiffies + HZ;
do
- if (get_status(port)->open)
+ if (get_status(port)->open) {
+ netif_start_queue(dev);
return 0;
+ }
while (time_after(timeout, jiffies));
printk(KERN_ERR "%s: unable to open port\n", dev->name);
if (get_status(port)->open)
printk(KERN_ERR "%s: unable to close port\n", dev->name);
+ netif_stop_queue(dev);
+
for (i = 0; i < TX_BUFFERS; i++) {
desc_t *desc = &get_status(port)->tx_descs[i];
unsigned long timeout;
u32 plx_phy; /* PLX PCI base address */
u32 mem_phy; /* memory PCI base addr */
- u8 *mem; /* memory virtual base addr */
+ u8 __iomem *mem; /* memory virtual base addr */
int i, ports, alloc_size;
#ifndef MODULE