/*
** System Bus Adapter (SBA) I/O MMU manager
**
-** (c) Copyright 2000 Grant Grundler
-** (c) Copyright 2000 Hewlett-Packard Company
+** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
+** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
+** (c) Copyright 2000-2004 Hewlett-Packard Company
**
** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
**
#include <linux/mm.h>
#include <linux/string.h>
-#undef PCI_DEBUG /* for ASSERT */
#include <linux/pci.h>
-#undef PCI_DEBUG
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/hardware.h> /* for register_parisc_driver() stuff */
#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+
#include <asm/runway.h> /* for proc_runway_root */
#include <asm/pdc.h> /* for PDC_MODEL_* */
+#include <asm/pdcpat.h> /* for is_pdc_pat() */
#include <asm/parisc-device.h>
+
+/* declared in arch/parisc/kernel/setup.c */
+extern struct proc_dir_entry * proc_mckinley_root;
+
#define MODULE_NAME "SBA"
#ifdef CONFIG_PROC_FS
#undef DEBUG_LARGE_SG_ENTRIES
#undef DEBUG_DMB_TRAP
-#define SBA_INLINE __inline__
-
#ifdef DEBUG_SBA_INIT
#define DBG_INIT(x...) printk(x)
#else
#define DBG_RES(x...)
#endif
+#if defined(CONFIG_64BIT)
+/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
+#define ZX1_SUPPORT
+#endif
+
+#define SBA_INLINE __inline__
+
+
/*
** The number of pdir entries to "free" before issueing
** a read to PCOM register to flush out PCOM writes.
#define DEFAULT_DMA_HINT_REG 0
#define ASTRO_RUNWAY_PORT 0x582
-#define ASTRO_ROPES_PORT 0x780
-
#define IKE_MERCED_PORT 0x803
-#define IKE_ROPES_PORT 0x781
-
#define REO_MERCED_PORT 0x804
-#define REO_ROPES_PORT 0x782
-
#define REOG_MERCED_PORT 0x805
-#define REOG_ROPES_PORT 0x783
+#define PLUTO_MCKINLEY_PORT 0x880
#define SBA_FUNC_ID 0x0000 /* function id */
#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
-#define IS_ASTRO(id) \
-(((id)->hversion == ASTRO_RUNWAY_PORT) || ((id)->hversion == ASTRO_ROPES_PORT))
-
-#define IS_IKE(id) \
-(((id)->hversion == IKE_MERCED_PORT) || ((id)->hversion == IKE_ROPES_PORT))
+#define IS_ASTRO(id) ((id)->hversion == ASTRO_RUNWAY_PORT)
+#define IS_IKE(id) ((id)->hversion == IKE_MERCED_PORT)
+#define IS_PLUTO(id) ((id)->hversion == PLUTO_MCKINLEY_PORT)
#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
-#define ASTRO_IOC_OFFSET 0x20000
-/* Ike's IOC's occupy functions 2 and 3 (not 0 and 1) */
-#define IKE_IOC_OFFSET(p) ((p+2)*SBA_FUNC_SIZE)
+#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
+#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
+/* Ike's IOC's occupy functions 2 and 3 */
+#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
#define IOC_CTRL 0x8 /* IOC_CTRL offset */
#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
#define IOC_CTRL_RM (1 << 8) /* Real Mode */
#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
+#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
+#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
-#define MAX_IOC 2 /* per Ike. Astro only has 1 */
+#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
+
+#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
/*
** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
** Firmware programs this stuff. Don't touch it.
*/
+#define LMMIO_DIRECT0_BASE 0x300
+#define LMMIO_DIRECT0_MASK 0x308
+#define LMMIO_DIRECT0_ROUTE 0x310
+
+#define LMMIO_DIST_BASE 0x360
+#define LMMIO_DIST_MASK 0x368
+#define LMMIO_DIST_ROUTE 0x370
+
#define IOS_DIST_BASE 0x390
#define IOS_DIST_MASK 0x398
#define IOS_DIST_ROUTE 0x3A0
#define ROPE6_CTL 0x230
#define ROPE7_CTL 0x238
+#define IOC_ROPE0_CFG 0x500 /* pluto only */
+#define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
+
+
+
#define HF_ENABLE 0x40
#define IOC_TCNFG 0x318
#define IOC_PDIR_BASE 0x320
-#define IOC_IOVA_SPACE_BASE 0 /* IOVA ranges start at 0 */
+/* AGP GART driver looks for this */
+#define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
+
/*
** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
** page since the Virtual Coherence Index has to be generated
** and updated for each page.
**
-** IOVP_SIZE could only be greater than PAGE_SIZE if we are
-** confident the drivers really only touch the next physical
-** page iff that driver instance owns it.
+** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
*/
#define IOVP_SIZE PAGE_SIZE
#define IOVP_SHIFT PAGE_SHIFT
struct ioc {
- unsigned long ioc_hpa; /* I/O MMU base address */
- char *res_map; /* resource map, bit == pdir entry */
- u64 *pdir_base; /* physical base address */
-
+ void __iomem *ioc_hpa; /* I/O MMU base address */
+ char *res_map; /* resource map, bit == pdir entry */
+ u64 *pdir_base; /* physical base address */
+ unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
+ unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
+#ifdef ZX1_SUPPORT
+ unsigned long iovp_mask; /* help convert IOVA to IOVP */
+#endif
unsigned long *res_hint; /* next avail IOVP - circular search */
spinlock_t res_lock;
- unsigned long hint_mask_pdir; /* bits used for DMA hints */
unsigned int res_bitshift; /* from the LEFT! */
unsigned int res_size; /* size of resource map in bytes */
+#ifdef SBA_HINT_SUPPORT
+/* FIXME : DMA HINTs not used */
+ unsigned long hint_mask_pdir; /* bits used for DMA hints */
unsigned int hint_shift_pdir;
+#endif
#if DELAYED_RESOURCE_CNT > 0
int saved_cnt;
struct sba_dma_pair {
/* STUFF We don't need in performance path */
unsigned int pdir_size; /* in bytes, determined by IOV Space size */
- unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
- unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
};
struct sba_device {
struct parisc_device *dev; /* dev found in bus walk */
struct parisc_device_id *iodc; /* data about dev from firmware */
const char *name;
- unsigned long sba_hpa; /* base address */
+ void __iomem *sba_hpa; /* base address */
spinlock_t sba_lock;
unsigned int flags; /* state/functionality enabled */
unsigned int hw_rev; /* HW revision of chip */
+ struct resource chip_resv; /* MMIO reserved for chip */
+ struct resource iommu_resv; /* MMIO reserved for iommu */
+
unsigned int num_ioc; /* number of on-board IOC's */
struct ioc ioc[MAX_IOC];
};
static unsigned long ioc_needs_fdc = 0;
-/* Ratio of Host MEM to IOV Space size */
-static unsigned long sba_mem_ratio = 8;
-
/* global count of IOMMUs in the system */
static unsigned int global_ioc_cnt = 0;
/* Looks nice and keeps the compiler happy */
#define SBA_DEV(d) ((struct sba_device *) (d))
+#ifdef SBA_AGP_SUPPORT
+static int reserve_sba_gart = 1;
+#endif
#define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
#define WRITE_REG32(val, addr) __raw_writel(cpu_to_le32(val), addr)
#define WRITE_REG64(val, addr) __raw_writeq(cpu_to_le64(val), addr)
-#ifdef __LP64__
+#ifdef CONFIG_64BIT
#define READ_REG(addr) READ_REG64(addr)
#define WRITE_REG(value, addr) WRITE_REG64(value, addr)
#else
#ifdef DEBUG_SBA_INIT
-/* NOTE: When __LP64__ isn't defined, READ_REG64() is two 32-bit reads */
+/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
/**
* sba_dump_ranges - debugging only - print ranges assigned to this IOA
* IO Adapter (aka Bus Converter).
*/
static void
-sba_dump_ranges(unsigned long hpa)
+sba_dump_ranges(void __iomem *hpa)
{
- DBG_INIT("SBA at 0x%lx\n", hpa);
+ DBG_INIT("SBA at 0x%p\n", hpa);
DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
*
* Print the size/location of the IO MMU PDIR.
*/
-static void
-sba_dump_tlb(unsigned long hpa)
+static void sba_dump_tlb(void __iomem *hpa)
{
- DBG_INIT("IO TLB at 0x%lx\n", hpa);
- DBG_INIT("IOC_IBASE : %Lx\n", READ_REG64(hpa+IOC_IBASE));
- DBG_INIT("IOC_IMASK : %Lx\n", READ_REG64(hpa+IOC_IMASK));
- DBG_INIT("IOC_TCNFG : %Lx\n", READ_REG64(hpa+IOC_TCNFG));
- DBG_INIT("IOC_PDIR_BASE: %Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
+ DBG_INIT("IO TLB at 0x%p\n", hpa);
+ DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
+ DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
+ DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
+ DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
DBG_INIT("\n");
}
-#endif
+#else
+#define sba_dump_ranges(x)
+#define sba_dump_tlb(x)
+#endif /* DEBUG_SBA_INIT */
#ifdef ASSERT_PDIR_SANITY
#define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
/* Convert from IOVP to IOVA and vice versa. */
-#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset) | ((hint_reg)<<(ioc->hint_shift_pdir)))
-#define SBA_IOVP(ioc,iova) ((iova) & ioc->hint_mask_pdir)
-/* FIXME : review these macros to verify correctness and usage */
+#ifdef ZX1_SUPPORT
+/* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
+#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
+#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
+#else
+/* only support Astro and ancestors. Saves a few cycles in key places */
+#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
+#define SBA_IOVP(ioc,iova) (iova)
+#endif
+
#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
-#define MKIOVP(dma_hint,pide) (dma_addr_t)((long)(dma_hint) | ((long)(pide) << IOVP_SHIFT))
-#define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset)
#define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
unsigned long pide = ~0UL;
- ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
- ASSERT(res_ptr < res_end);
if (bits_wanted > (BITS_PER_LONG/2)) {
/* Search word at a time - no mask needed */
for(; res_ptr < res_end; ++res_ptr) {
while(res_ptr < res_end)
{
DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
- ASSERT(0 != mask);
- if(0 == ((*res_ptr) & mask)) {
+ WARN_ON(mask == 0);
+ if(((*res_ptr) & mask) == 0) {
*res_ptr |= mask; /* mark resources busy! */
pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
pide <<= 3; /* convert to bit address */
}
mask >>= o;
bitshiftcnt += o;
- if (0 == mask) {
+ if (mask == 0) {
mask = RESMAP_MASK(bits_wanted);
bitshiftcnt=0;
res_ptr++;
#endif
unsigned long pide;
- ASSERT(pages_needed);
- ASSERT((pages_needed * IOVP_SIZE) <= DMA_CHUNK_SIZE);
- ASSERT(pages_needed <= BITS_PER_LONG);
- ASSERT(0 == (size & ~IOVP_MASK));
-
- /*
- ** "seek and ye shall find"...praying never hurts either...
- ** ggg sacrifices another 710 to the computer gods.
- */
-
pide = sba_search_bitmap(ioc, pages_needed);
if (pide >= (ioc->res_size << 3)) {
pide = sba_search_bitmap(ioc, pages_needed);
if (pide >= (ioc->res_size << 3))
- panic("%s: I/O MMU @ %lx is out of mapping resources\n",
+ panic("%s: I/O MMU @ %p is out of mapping resources\n",
__FILE__, ioc->ioc_hpa);
}
ioc->used_pages -= bits_not_wanted;
#endif
- ASSERT(m != 0);
- ASSERT(bits_not_wanted);
- ASSERT((bits_not_wanted * IOVP_SIZE) <= DMA_CHUNK_SIZE);
- ASSERT(bits_not_wanted <= BITS_PER_LONG);
- ASSERT((*res_ptr & m) == m); /* verify same bits are set */
*res_ptr &= ~m;
}
*
***************************************************************/
+#ifdef SBA_HINT_SUPPORT
#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
-
+#endif
typedef unsigned long space_t;
#define KERNEL_SPACE 0
/**
* sba_io_pdir_entry - fill in one IO PDIR entry
* @pdir_ptr: pointer to IO PDIR entry
- * @sid: process Space ID
+ * @sid: process Space ID - currently only support KERNEL_SPACE
* @vba: Virtual CPU address of buffer to map
+ * @hint: DMA hint set to use for this mapping
*
* SBA Mapping Routine
*
* Given a virtual address (vba, arg2) and space id, (sid, arg1)
* sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
- * pdir_ptr (arg0). Each IO Pdir entry consists of 8 bytes as
- * shown below (MSB == bit 0):
+ * pdir_ptr (arg0).
+ * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
+ * for Astro/Ike looks like:
+ *
*
* 0 19 51 55 63
* +-+---------------------+----------------------------------+----+--------+
* |V| U | PPN[43:12] | U | VI |
* +-+---------------------+----------------------------------+----+--------+
*
- * V == Valid Bit
+ * Pluto is basically identical, supports fewer physical address bits:
+ *
+ * 0 23 51 55 63
+ * +-+------------------------+-------------------------------+----+--------+
+ * |V| U | PPN[39:12] | U | VI |
+ * +-+------------------------+-------------------------------+----+--------+
+ *
+ * V == Valid Bit (Most Significant Bit is bit 0)
* U == Unused
* PPN == Physical Page Number
* VI == Virtual Index (aka Coherent Index)
*
- * The physical address fields are filled with the results of the LPA
- * instruction. The virtual index field is filled with the results of
- * of the LCI (Load Coherence Index) instruction. The 8 bits used for
- * the virtual index are bits 12:19 of the value returned by LCI.
+ * LPA instruction output is put into PPN field.
+ * LCI (Load Coherence Index) instruction provides the "VI" bits.
*
- * We need to pre-swap the bytes since PCX-W is Big Endian.
+ * We pre-swap the bytes since PCX-W is Big Endian and the
+ * IOMMU uses little endian for the pdir.
*/
-
void SBA_INLINE
sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
unsigned long hint)
u64 pa; /* physical address */
register unsigned ci; /* coherent index */
- /* We currently only support kernel addresses.
- * fdc instr below will need to reload sr1 with KERNEL_SPACE
- * once we try to support direct DMA to user space.
- */
- ASSERT(sid == KERNEL_SPACE);
-
pa = virt_to_phys(vba);
- pa &= ~4095ULL; /* clear out offset bits */
+ pa &= IOVP_MASK;
mtsp(sid,1);
asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
* (bit #61, big endian), we have to flush and sync every time
* IO-PDIR is changed in Ike/Astro.
*/
- if (ioc_needs_fdc) {
- asm volatile("fdc 0(%%sr1,%0)\n\tsync" : : "r" (pdir_ptr));
- }
+ if (ioc_needs_fdc)
+ asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
}
sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
{
u32 iovp = (u32) SBA_IOVP(ioc,iova);
-
- /* Even though this is a big-endian machine, the entries
- ** in the iopdir are little endian. That's why we clear the byte
- ** at +7 instead of at +0.
- */
- int off = PDIR_INDEX(iovp)*sizeof(u64)+7;
-
- /* Must be non-zero and rounded up */
- ASSERT(byte_cnt > 0);
- ASSERT(0 == (byte_cnt & ~IOVP_MASK));
+ u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
#ifdef ASSERT_PDIR_SANITY
- /* Assert first pdir entry is set */
- if (0x80 != (((u8 *) ioc->pdir_base)[off])) {
+ /* Assert first pdir entry is set.
+ **
+ ** Even though this is a big-endian machine, the entries
+ ** in the iopdir are little endian. That's why we look at
+ ** the byte at +7 instead of at +0.
+ */
+ if (0x80 != (((u8 *) pdir_ptr)[7])) {
sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
}
#endif
- if (byte_cnt <= IOVP_SIZE)
+ if (byte_cnt > IOVP_SIZE)
{
- ASSERT( off < ioc->pdir_size);
-
- iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
-
- /*
- ** clear I/O PDIR entry "valid" bit
- ** Do NOT clear the rest - save it for debugging.
- ** We should only clear bits that have previously
- ** been enabled.
- */
- ((u8 *)(ioc->pdir_base))[off] = 0;
- } else {
- u32 t = get_order(byte_cnt) + PAGE_SHIFT;
+#if 0
+ unsigned long entries_per_cacheline = ioc_needs_fdc ?
+ L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
+ - (unsigned long) pdir_ptr;
+ : 262144;
+#endif
- iovp |= t;
- ASSERT(t <= 31); /* 2GB! Max value of "size" field */
+ /* set "size" field for PCOM */
+ iovp |= get_order(byte_cnt) + PAGE_SHIFT;
do {
- /* verify this pdir entry is enabled */
- ASSERT(0x80 == (((u8 *) ioc->pdir_base)[off] & 0x80));
/* clear I/O Pdir entry "valid" bit first */
- ((u8 *)(ioc->pdir_base))[off] = 0;
- off += sizeof(u64);
+ ((u8 *) pdir_ptr)[7] = 0;
+ if (ioc_needs_fdc) {
+ asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
+#if 0
+ entries_per_cacheline = L1_CACHE_SHIFT - 3;
+#endif
+ }
+ pdir_ptr++;
byte_cnt -= IOVP_SIZE;
- } while (byte_cnt > 0);
- }
+ } while (byte_cnt > IOVP_SIZE);
+ } else
+ iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
+
+ /*
+ ** clear I/O PDIR entry "valid" bit.
+ ** We have to R/M/W the cacheline regardless how much of the
+ ** pdir entry that we clobber.
+ ** The rest of the entry would be useful for debugging if we
+ ** could dump core on HPMC.
+ */
+ ((u8 *) pdir_ptr)[7] = 0;
+ if (ioc_needs_fdc)
+ asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
- WRITE_REG(iovp, ioc->ioc_hpa+IOC_PCOM);
+ WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
}
/**
*
* See Documentation/DMA-mapping.txt
*/
-static int
-sba_dma_supported( struct device *dev, u64 mask)
+static int sba_dma_supported( struct device *dev, u64 mask)
{
+ struct ioc *ioc;
+
if (dev == NULL) {
printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
BUG();
return(0);
}
- /* only support 32-bit PCI devices - no DAC support (yet) */
- return((int) (mask == 0xffffffffUL));
+ /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first,
+ * then fall back to 32-bit if that fails.
+ * We are just "encouraging" 32-bit DMA masks here since we can
+ * never allow IOMMU bypass unless we add special support for ZX1.
+ */
+ if (mask > ~0U)
+ return 0;
+
+ ioc = GET_IOC(dev);
+
+ /*
+ * check if mask is >= than the current max IO Virt Address
+ * The max IO Virt address will *always* < 30 bits.
+ */
+ return((int)(mask >= (ioc->ibase - 1 +
+ (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
}
u64 *pdir_start;
int pide;
- ASSERT(size > 0);
- ASSERT(size <= DMA_CHUNK_SIZE);
-
ioc = GET_IOC(dev);
- ASSERT(ioc);
/* save offset bits */
offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
pide = sba_alloc_range(ioc, size);
iovp = (dma_addr_t) pide << IOVP_SHIFT;
- DBG_RUN("%s() 0x%p -> 0x%lx",
+ DBG_RUN("%s() 0x%p -> 0x%lx\n",
__FUNCTION__, addr, (long) iovp | offset);
pdir_start = &(ioc->pdir_base[pide]);
while (size > 0) {
- ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
- DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
+ DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
pdir_start,
(u8) (((u8 *) pdir_start)[7]),
(u8) (((u8 *) pdir_start)[6]),
size -= IOVP_SIZE;
pdir_start++;
}
- /* form complete address */
+
+ /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
+ if (ioc_needs_fdc)
+ asm volatile("sync" : : );
+
#ifdef ASSERT_PDIR_SANITY
sba_check_pdir(ioc,"Check after sba_map_single()");
#endif
spin_unlock_irqrestore(&ioc->res_lock, flags);
+
+ /* form complete address */
return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
}
unsigned long flags;
dma_addr_t offset;
- ioc = GET_IOC(dev);
- ASSERT(ioc);
+ DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
+ ioc = GET_IOC(dev);
offset = iova & ~IOVP_MASK;
-
- DBG_RUN("%s() iovp 0x%lx/%x\n",
- __FUNCTION__, (long) iova, size);
-
iova ^= offset; /* clear offset bits */
size += offset;
size = ROUNDUP(size, IOVP_SIZE);
ioc->usingle_pages += size >> IOVP_SHIFT;
#endif
+ sba_mark_invalid(ioc, iova, size);
+
#if DELAYED_RESOURCE_CNT > 0
+ /* Delaying when we re-use a IO Pdir entry reduces the number
+ * of MMIO reads needed to flush writes to the PCOM register.
+ */
d = &(ioc->saved[ioc->saved_cnt]);
d->iova = iova;
d->size = size;
if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
int cnt = ioc->saved_cnt;
while (cnt--) {
- sba_mark_invalid(ioc, d->iova, d->size);
sba_free_range(ioc, d->iova, d->size);
d--;
}
ioc->saved_cnt = 0;
+
READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
}
#else /* DELAYED_RESOURCE_CNT == 0 */
- sba_mark_invalid(ioc, iova, size);
sba_free_range(ioc, iova, size);
+
+ /* If fdc's were issued, force fdc's to be visible now */
+ if (ioc_needs_fdc)
+ asm volatile("sync" : : );
+
READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
#endif /* DELAYED_RESOURCE_CNT == 0 */
+
spin_unlock_irqrestore(&ioc->res_lock, flags);
/* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
* See Documentation/DMA-mapping.txt
*/
static void *sba_alloc_consistent(struct device *hwdev, size_t size,
- dma_addr_t *dma_handle, int gfp)
+ dma_addr_t *dma_handle, gfp_t gfp)
{
void *ret;
DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
ioc = GET_IOC(dev);
- ASSERT(ioc);
/* Fast path single entry scatterlists. */
if (nents == 1) {
*/
filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
+ /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
+ if (ioc_needs_fdc)
+ asm volatile("sync" : : );
+
#ifdef ASSERT_PDIR_SANITY
if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
{
spin_unlock_irqrestore(&ioc->res_lock, flags);
- ASSERT(coalesced == filled);
DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
return filled;
__FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
ioc = GET_IOC(dev);
- ASSERT(ioc);
#ifdef SBA_COLLECT_STATS
ioc->usg_calls++;
unsigned long pdir_order = get_order(pdir_size);
pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
- if (NULL == (void *) pdir_base)
- panic("sba_ioc_init() could not allocate I/O Page Table\n");
+ if (NULL == (void *) pdir_base) {
+ panic("%s() could not allocate I/O Page Table\n",
+ __FUNCTION__);
+ }
/* If this is not PA8700 (PCX-W2)
** OR newer than ver 2.2
return (void *) pdir_base;
}
+static struct device *next_device(struct klist_iter *i)
+{
+ struct klist_node * n = klist_next(i);
+ return n ? container_of(n, struct device, knode_parent) : NULL;
+}
+
+/* setup Mercury or Elroy IBASE/IMASK registers. */
+static void
+setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
+{
+ /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
+ extern void lba_set_iregs(struct parisc_device *, u32, u32);
+ struct device *dev;
+ struct klist_iter i;
+
+ klist_iter_init(&sba->dev.klist_children, &i);
+ while ((dev = next_device(&i))) {
+ struct parisc_device *lba = to_parisc_device(dev);
+ int rope_num = (lba->hpa.start >> 13) & 0xf;
+ if (rope_num >> 3 == ioc_num)
+ lba_set_iregs(lba, ioc->ibase, ioc->imask);
+ }
+ klist_iter_exit(&i);
+}
static void
-sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
+sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
{
- /* lba_set_iregs() is in arch/parisc/kernel/lba_pci.c */
- extern void lba_set_iregs(struct parisc_device *, u32, u32);
+ u32 iova_space_mask;
+ u32 iova_space_size;
+ int iov_order, tcnfg;
+#ifdef SBA_AGP_SUPPORT
+ int agp_found = 0;
+#endif
+ /*
+ ** Firmware programs the base and size of a "safe IOVA space"
+ ** (one that doesn't overlap memory or LMMIO space) in the
+ ** IBASE and IMASK registers.
+ */
+ ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
+ iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
+
+ if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
+ printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
+ iova_space_size /= 2;
+ }
+
+ /*
+ ** iov_order is always based on a 1GB IOVA space since we want to
+ ** turn on the other half for AGP GART.
+ */
+ iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
+ ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
+
+ DBG_INIT("%s() hpa 0x%lx IOV %dMB (%d bits)\n",
+ __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20,
+ iov_order + PAGE_SHIFT);
+
+ ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
+ get_order(ioc->pdir_size));
+ if (!ioc->pdir_base)
+ panic("Couldn't allocate I/O Page Table\n");
+
+ memset(ioc->pdir_base, 0, ioc->pdir_size);
+
+ DBG_INIT("%s() pdir %p size %x\n",
+ __FUNCTION__, ioc->pdir_base, ioc->pdir_size);
+
+#ifdef SBA_HINT_SUPPORT
+ ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
+ ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
+
+ DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
+ ioc->hint_shift_pdir, ioc->hint_mask_pdir);
+#endif
+
+ WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
+ WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
+
+ /* build IMASK for IOC and Elroy */
+ iova_space_mask = 0xffffffff;
+ iova_space_mask <<= (iov_order + PAGE_SHIFT);
+ ioc->imask = iova_space_mask;
+#ifdef ZX1_SUPPORT
+ ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
+#endif
+ sba_dump_tlb(ioc->ioc_hpa);
+
+ setup_ibase_imask(sba, ioc, ioc_num);
+
+ WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
+
+#ifdef CONFIG_64BIT
+ /*
+ ** Setting the upper bits makes checking for bypass addresses
+ ** a little faster later on.
+ */
+ ioc->imask |= 0xFFFFFFFF00000000UL;
+#endif
+
+ /* Set I/O PDIR Page size to system page size */
+ switch (PAGE_SHIFT) {
+ case 12: tcnfg = 0; break; /* 4K */
+ case 13: tcnfg = 1; break; /* 8K */
+ case 14: tcnfg = 2; break; /* 16K */
+ case 16: tcnfg = 3; break; /* 64K */
+ default:
+ panic(__FILE__ "Unsupported system page size %d",
+ 1 << PAGE_SHIFT);
+ break;
+ }
+ WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
+
+ /*
+ ** Program the IOC's ibase and enable IOVA translation
+ ** Bit zero == enable bit.
+ */
+ WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
+
+ /*
+ ** Clear I/O TLB of any possible entries.
+ ** (Yes. This is a bit paranoid...but so what)
+ */
+ WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
+
+#ifdef SBA_AGP_SUPPORT
+ /*
+ ** If an AGP device is present, only use half of the IOV space
+ ** for PCI DMA. Unfortunately we can't know ahead of time
+ ** whether GART support will actually be used, for now we
+ ** can just key on any AGP device found in the system.
+ ** We program the next pdir index after we stop w/ a key for
+ ** the GART code to handshake on.
+ */
+ device=NULL;
+ for (lba = sba->child; lba; lba = lba->sibling) {
+ if (IS_QUICKSILVER(lba))
+ break;
+ }
+
+ if (lba) {
+ DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__);
+ ioc->pdir_size /= 2;
+ ((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE;
+ } else {
+ DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__);
+ }
+#endif /* 0 */
+
+}
+static void
+sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
+{
u32 iova_space_size, iova_space_mask;
- int pdir_size, iov_order;
- unsigned long physmem;
- struct parisc_device *lba;
+ unsigned int pdir_size, iov_order;
/*
** Determine IOVA Space size from memory size.
** for DMA hints - ergo only 30 bits max.
*/
- physmem = num_physpages << PAGE_SHIFT;
- iova_space_size = (u32) (physmem/(sba_mem_ratio*global_ioc_cnt));
+ iova_space_size = (u32) (num_physpages/global_ioc_cnt);
/* limit IOVA space size to 1MB-1GB */
- if (iova_space_size < 1024*1024) {
- iova_space_size = 1024*1024;
+ if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
+ iova_space_size = 1 << (20 - PAGE_SHIFT);
}
-#ifdef __LP64__
- else if (iova_space_size > 512*1024*1024) {
- iova_space_size = 512*1024*1024;
+ else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
+ iova_space_size = 1 << (30 - PAGE_SHIFT);
}
-#endif
/*
** iova space must be log2() in size.
** thus, pdir/res_map will also be log2().
** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
*/
- iov_order = get_order(iova_space_size >> (IOVP_SHIFT-PAGE_SHIFT));
- ASSERT(iov_order <= (30 - IOVP_SHIFT)); /* iova_space_size <= 1GB */
- ASSERT(iov_order >= (20 - IOVP_SHIFT)); /* iova_space_size >= 1MB */
- iova_space_size = 1 << (iov_order + IOVP_SHIFT);
+ iov_order = get_order(iova_space_size << PAGE_SHIFT);
+
+ /* iova_space_size is now bytes, not pages */
+ iova_space_size = 1 << (iov_order + PAGE_SHIFT);
ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
- ASSERT(pdir_size < 4*1024*1024); /* max pdir size == 2MB */
+ DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
+ __FUNCTION__,
+ ioc->ioc_hpa,
+ (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
+ iova_space_size>>20,
+ iov_order + PAGE_SHIFT);
- /* Verify it's a power of two */
- ASSERT((1 << get_order(pdir_size)) == (pdir_size >> PAGE_SHIFT));
+ ioc->pdir_base = sba_alloc_pdir(pdir_size);
- DBG_INIT("%s() hpa 0x%lx mem %dMB IOV %dMB (%d bits) PDIR size 0x%0x\n",
- __FUNCTION__, ioc->ioc_hpa, (int) (physmem>>20),
- iova_space_size>>20, iov_order + PAGE_SHIFT, pdir_size);
+ DBG_INIT("%s() pdir %p size %x\n",
+ __FUNCTION__, ioc->pdir_base, pdir_size);
+#ifdef SBA_HINT_SUPPORT
/* FIXME : DMA HINTs not used */
ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
- ioc->pdir_base = sba_alloc_pdir(pdir_size);
-
- DBG_INIT("%s() pdir %p size %x hint_shift_pdir %x hint_mask_pdir %lx\n",
- __FUNCTION__, ioc->pdir_base, pdir_size,
- ioc->hint_shift_pdir, ioc->hint_mask_pdir);
+ DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
+ ioc->hint_shift_pdir, ioc->hint_mask_pdir);
+#endif
- ASSERT((((unsigned long) ioc->pdir_base) & PAGE_MASK) == (unsigned long) ioc->pdir_base);
WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
/* build IMASK for IOC and Elroy */
** On C3000 w/512MB mem, HP-UX 10.20 reports:
** ibase=0, imask=0xFE000000, size=0x2000000.
*/
- ioc->ibase = IOC_IOVA_SPACE_BASE | 1; /* bit 0 == enable bit */
+ ioc->ibase = 0;
ioc->imask = iova_space_mask; /* save it */
+#ifdef ZX1_SUPPORT
+ ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
+#endif
DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
__FUNCTION__, ioc->ibase, ioc->imask);
** can't reprogram them the way drivers want.
*/
- /*
- ** setup Elroy IBASE/IMASK registers as well.
- */
- for (lba = sba->child; lba; lba = lba->sibling) {
- int rope_num = (lba->hpa >> 13) & 0xf;
- if (rope_num >> 3 == ioc_num)
- lba_set_iregs(lba, ioc->ibase, ioc->imask);
- }
+ setup_ibase_imask(sba, ioc, ioc_num);
/*
** Program the IOC's ibase and enable IOVA translation
*/
- WRITE_REG(ioc->ibase, ioc->ioc_hpa+IOC_IBASE);
+ WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
/* Set I/O PDIR Page size to 4K */
*/
WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
+ ioc->ibase = 0; /* used by SBA_IOVA and related macros */
+
DBG_INIT("%s() DONE\n", __FUNCTION__);
}
**
**************************************************************************/
-static void
-sba_hw_init(struct sba_device *sba_dev)
+static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
+{
+ return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
+}
+
+static void sba_hw_init(struct sba_device *sba_dev)
{
int i;
int num_ioc;
if (!is_pdc_pat()) {
/* Shutdown the USB controller on Astro-based workstations.
** Once we reprogram the IOMMU, the next DMA performed by
- ** USB will HPMC the box.
+ ** USB will HPMC the box. USB is only enabled if a
+ ** keyboard is present and found.
+ **
+ ** With serial console, j6k v5.0 firmware says:
+ ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
+ **
+ ** FIXME: Using GFX+USB console at power up but direct
+ ** linux to serial console is still broken.
+ ** USB could generate DMA so we must reset USB.
+ ** The proper sequence would be:
+ ** o block console output
+ ** o reset USB device
+ ** o reprogram serial port
+ ** o unblock console output
*/
- pdc_io_reset_devices();
+ if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
+ pdc_io_reset_devices();
+ }
- /*
- ** XXX May need something more sophisticated to deal
- ** with DMA from LAN. Maybe use page zero boot device
- ** as a handle to talk to PDC about which device to
- ** shutdown. This also needs to work for is_pdc_pat().
- */
}
- ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
- DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
- __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
- ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
- ioc_ctl |= IOC_CTRL_TC; /* Astro: firmware enables this */
- WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
+#if 0
+printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
+ PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
+
+ /*
+ ** Need to deal with DMA from LAN.
+ ** Maybe use page zero boot device as a handle to talk
+ ** to PDC about which device to shutdown.
+ **
+ ** Netbooting, j6k v5.0 firmware says:
+ ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
+ ** ARGH! invalid class.
+ */
+ if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
+ && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
+ pdc_io_reset();
+ }
+#endif
+
+ if (!IS_PLUTO(sba_dev->iodc)) {
+ ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
+ DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
+ __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
+ ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
+ ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
+ /* j6700 v1.6 firmware sets 0x294f */
+ /* A500 firmware sets 0x4d */
+
+ WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
#ifdef DEBUG_SBA_INIT
- ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
- DBG_INIT(" 0x%Lx\n", ioc_ctl);
+ ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
+ DBG_INIT(" 0x%Lx\n", ioc_ctl);
#endif
+ } /* if !PLUTO */
if (IS_ASTRO(sba_dev->iodc)) {
+ int err;
/* PAT_PDC (L-class) also reports the same goofy base */
- sba_dev->ioc[0].ioc_hpa = ASTRO_IOC_OFFSET;
+ sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
num_ioc = 1;
+
+ sba_dev->chip_resv.name = "Astro Intr Ack";
+ sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
+ sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
+ err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
+ BUG_ON(err < 0);
+
+ } else if (IS_PLUTO(sba_dev->iodc)) {
+ int err;
+
+ /* We use a negative value for IOC HPA so it gets
+ * corrected when we add it with IKE's IOC offset.
+ * Doesnt look clean, but fewer code.
+ */
+ sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
+ num_ioc = 1;
+
+ sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
+ sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
+ sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
+ err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
+ WARN_ON(err < 0);
+
+ sba_dev->iommu_resv.name = "IOVA Space";
+ sba_dev->iommu_resv.start = 0x40000000UL;
+ sba_dev->iommu_resv.end = 0x50000000UL - 1;
+ err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
+ WARN_ON(err < 0);
} else {
- sba_dev->ioc[0].ioc_hpa = sba_dev->ioc[1].ioc_hpa = 0;
+ /* IS_IKE (ie N-class, L3000, L1500) */
+ sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
+ sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
num_ioc = 2;
+
+ /* TODO - LOOKUP Ike/Stretch chipset mem map */
}
+ /* XXX: What about Reo? */
sba_dev->num_ioc = num_ioc;
for (i = 0; i < num_ioc; i++) {
- sba_dev->ioc[i].ioc_hpa += sba_dev->sba_hpa + IKE_IOC_OFFSET(i);
+ unsigned long ioc_hpa = sba_dev->ioc[i].ioc_hpa;
+ unsigned int j;
- /*
- ** Make sure the box crashes if we get any errors on a rope.
- */
- WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE0_CTL);
- WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE1_CTL);
- WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE2_CTL);
- WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE3_CTL);
- WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE4_CTL);
- WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE5_CTL);
- WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE6_CTL);
- WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
-
- /* flush out the writes */
+ for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
+
+ /*
+ * Clear ROPE(N)_CONFIG AO bit.
+ * Disables "NT Ordering" (~= !"Relaxed Ordering")
+ * Overrides bit 1 in DMA Hint Sets.
+ * Improves netperf UDP_STREAM by ~10% for bcm5701.
+ */
+ if (IS_PLUTO(sba_dev->iodc)) {
+ unsigned long rope_cfg, cfg_val;
+
+ rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
+ cfg_val = READ_REG(rope_cfg);
+ cfg_val &= ~IOC_ROPE_AO;
+ WRITE_REG(cfg_val, rope_cfg);
+ }
+
+ /*
+ ** Make sure the box crashes on rope errors.
+ */
+ WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
+ }
+
+ /* flush out the last writes */
READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
- sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
+ DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
+ i,
+ READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
+ READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
+ );
+ DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
+ READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
+ READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
+ );
+
+ if (IS_PLUTO(sba_dev->iodc)) {
+ sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
+ } else {
+ sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
+ }
}
}
__FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
}
- sba_dev->sba_lock = SPIN_LOCK_UNLOCKED;
+ spin_lock_init(&sba_dev->sba_lock);
ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
#ifdef DEBUG_SBA_INIT
}
#ifdef CONFIG_PROC_FS
-static int sba_proc_info(char *buf, char **start, off_t offset, int len)
+static int sba_proc_info(struct seq_file *m, void *p)
{
struct sba_device *sba_dev = sba_list;
struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
#ifdef SBA_COLLECT_STATS
- unsigned long i = 0, avg = 0, min, max;
+ unsigned long avg = 0, min, max;
#endif
+ int i, len = 0;
- sprintf(buf, "%s rev %d.%d\n",
+ len += seq_printf(m, "%s rev %d.%d\n",
sba_dev->name,
(sba_dev->hw_rev & 0x7) + 1,
(sba_dev->hw_rev & 0x18) >> 3
);
- sprintf(buf, "%sIO PDIR size : %d bytes (%d entries)\n",
- buf,
+ len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
(int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
total_pages);
- sprintf(buf, "%sResource bitmap : %d bytes (%d pages)\n",
- buf, ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
+ len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
+ ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
+
+ len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
+ READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
+ READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
+ READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
+ );
+
+ for (i=0; i<4; i++)
+ len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i,
+ READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
+ READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
+ READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
+ );
#ifdef SBA_COLLECT_STATS
- sprintf(buf, "%sIO PDIR entries : %ld free %ld used (%d%%)\n", buf,
+ len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
total_pages - ioc->used_pages, ioc->used_pages,
(int) (ioc->used_pages * 100 / total_pages));
if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
}
avg /= SBA_SEARCH_SAMPLE;
- sprintf(buf, "%s Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
- buf, min, avg, max);
+ len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
+ min, avg, max);
- sprintf(buf, "%spci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
- buf, ioc->msingle_calls, ioc->msingle_pages,
+ len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
+ ioc->msingle_calls, ioc->msingle_pages,
(int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
/* KLUGE - unmap_sg calls unmap_single for each mapped page */
min = ioc->usingle_calls;
max = ioc->usingle_pages - ioc->usg_pages;
- sprintf(buf, "%spci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
- buf, min, max,
- (int) ((max * 1000)/min));
+ len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
+ min, max, (int) ((max * 1000)/min));
- sprintf(buf, "%spci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
- buf, ioc->msg_calls, ioc->msg_pages,
+ len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
+ ioc->msg_calls, ioc->msg_pages,
(int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
- sprintf(buf, "%spci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
- buf, ioc->usg_calls, ioc->usg_pages,
+ len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
+ ioc->usg_calls, ioc->usg_pages,
(int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
#endif
- return strlen(buf);
+ return 0;
}
-#if 0
-/* XXX too much output - exceeds 4k limit and needs to be re-written */
static int
-sba_resource_map(char *buf, char **start, off_t offset, int len)
+sba_proc_open(struct inode *i, struct file *f)
+{
+ return single_open(f, &sba_proc_info, NULL);
+}
+
+static struct file_operations sba_proc_fops = {
+ .owner = THIS_MODULE,
+ .open = sba_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+static int
+sba_proc_bitmap_info(struct seq_file *m, void *p)
{
struct sba_device *sba_dev = sba_list;
- struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Mutli-IOC suppoer! */
+ struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
unsigned int *res_ptr = (unsigned int *)ioc->res_map;
- int i;
+ int i, len = 0;
- buf[0] = '\0';
- for(i = 0; i < (ioc->res_size / sizeof(unsigned int)); ++i, ++res_ptr) {
+ for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) {
if ((i & 7) == 0)
- strcat(buf,"\n ");
- sprintf(buf, "%s %08x", buf, *res_ptr);
+ len += seq_printf(m, "\n ");
+ len += seq_printf(m, " %08x", *res_ptr);
}
- strcat(buf, "\n");
+ len += seq_printf(m, "\n");
- return strlen(buf);
+ return 0;
}
-#endif /* 0 */
+
+static int
+sba_proc_bitmap_open(struct inode *i, struct file *f)
+{
+ return single_open(f, &sba_proc_bitmap_info, NULL);
+}
+
+static struct file_operations sba_proc_bitmap_fops = {
+ .owner = THIS_MODULE,
+ .open = sba_proc_bitmap_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
#endif /* CONFIG_PROC_FS */
static struct parisc_device_id sba_tbl[] = {
{ HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
{ HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
{ HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
-/* These two entries commented out because we don't find them in a
- * buswalk yet. If/when we do, they would cause us to think we had
- * many more SBAs then we really do.
- * { HPHW_BCPORT, HVERSION_REV_ANY_ID, ASTRO_ROPES_PORT, 0xc },
- * { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_ROPES_PORT, 0xc },
- */
+ { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
{ 0, }
};
};
/*
-** Determine if lba should claim this chip (return 0) or not (return 1).
+** Determine if sba should claim this chip (return 0) or not (return 1).
** If so, initialize the chip and tell other partners in crime they
** have work to do.
*/
u32 func_class;
int i;
char *version;
+ void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
+ struct proc_dir_entry *info_entry, *bitmap_entry, *root;
-#ifdef DEBUG_SBA_INIT
- sba_dump_ranges(dev->hpa);
-#endif
+ sba_dump_ranges(sba_addr);
/* Read HW Rev First */
- func_class = READ_REG(dev->hpa + SBA_FCLASS);
+ func_class = READ_REG(sba_addr + SBA_FCLASS);
if (IS_ASTRO(&dev->id)) {
unsigned long fclass;
static char astro_rev[]="Astro ?.?";
/* Astro is broken...Read HW Rev First */
- fclass = READ_REG(dev->hpa);
+ fclass = READ_REG(sba_addr);
astro_rev[6] = '1' + (char) (fclass & 0x7);
astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
version = astro_rev;
} else if (IS_IKE(&dev->id)) {
- static char ike_rev[]="Ike rev ?";
-
+ static char ike_rev[] = "Ike rev ?";
ike_rev[8] = '0' + (char) (func_class & 0xff);
version = ike_rev;
+ } else if (IS_PLUTO(&dev->id)) {
+ static char pluto_rev[]="Pluto ?.?";
+ pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
+ pluto_rev[8] = '0' + (char) (func_class & 0x0f);
+ version = pluto_rev;
} else {
- static char reo_rev[]="REO rev ?";
-
+ static char reo_rev[] = "REO rev ?";
reo_rev[8] = '0' + (char) (func_class & 0xff);
version = reo_rev;
}
if (!global_ioc_cnt) {
global_ioc_cnt = count_parisc_driver(&sba_driver);
- /* Only Astro has one IOC per SBA */
- if (!IS_ASTRO(&dev->id))
+ /* Astro and Pluto have one IOC per SBA */
+ if ((!IS_ASTRO(&dev->id)) || (!IS_PLUTO(&dev->id)))
global_ioc_cnt *= 2;
}
printk(KERN_INFO "%s found %s at 0x%lx\n",
- MODULE_NAME, version, dev->hpa);
-
-#ifdef DEBUG_SBA_INIT
- sba_dump_tlb(dev->hpa);
-#endif
+ MODULE_NAME, version, dev->hpa.start);
- sba_dev = kmalloc(sizeof(struct sba_device), GFP_KERNEL);
- if (NULL == sba_dev) {
+ sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
+ if (!sba_dev) {
printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
- return(1);
+ return -ENOMEM;
}
- dev->sysdata = (void *) sba_dev;
- memset(sba_dev, 0, sizeof(struct sba_device));
+ parisc_set_drvdata(dev, sba_dev);
for(i=0; i<MAX_IOC; i++)
spin_lock_init(&(sba_dev->ioc[i].res_lock));
sba_dev->hw_rev = func_class;
sba_dev->iodc = &dev->id;
sba_dev->name = dev->name;
- sba_dev->sba_hpa = dev->hpa; /* faster access */
+ sba_dev->sba_hpa = sba_addr;
sba_get_pat_resources(sba_dev);
sba_hw_init(sba_dev);
hppa_dma_ops = &sba_ops;
#ifdef CONFIG_PROC_FS
- if (IS_ASTRO(&dev->id)) {
- create_proc_info_entry("Astro", 0, proc_runway_root, sba_proc_info);
- } else if (IS_IKE(&dev->id)) {
- create_proc_info_entry("Ike", 0, proc_runway_root, sba_proc_info);
- } else {
- create_proc_info_entry("Reo", 0, proc_runway_root, sba_proc_info);
+ switch (dev->id.hversion) {
+ case PLUTO_MCKINLEY_PORT:
+ root = proc_mckinley_root;
+ break;
+ case ASTRO_RUNWAY_PORT:
+ case IKE_MERCED_PORT:
+ default:
+ root = proc_runway_root;
+ break;
}
-#if 0
- create_proc_info_entry("bitmap", 0, proc_runway_root, sba_resource_map);
-#endif
+
+ info_entry = create_proc_entry("sba_iommu", 0, root);
+ bitmap_entry = create_proc_entry("sba_iommu-bitmap", 0, root);
+
+ if (info_entry)
+ info_entry->proc_fops = &sba_proc_fops;
+
+ if (bitmap_entry)
+ bitmap_entry->proc_fops = &sba_proc_bitmap_fops;
#endif
+
parisc_vmerge_boundary = IOVP_SIZE;
parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
-
+ parisc_has_iommu();
return 0;
}
* sba_get_iommu - Assign the iommu pointer for the pci bus controller.
* @dev: The parisc device.
*
- * This function searches through the registerd IOMMU's and returns the
- * appropriate IOMMU data for the given parisc PCI controller.
+ * Returns the appropriate IOMMU data for the given parisc PCI controller.
+ * This is cached and used later for PCI DMA Mapping.
*/
void * sba_get_iommu(struct parisc_device *pci_hba)
{
- struct sba_device *sba = (struct sba_device *) pci_hba->parent->sysdata;
- char t = pci_hba->parent->id.hw_type;
+ struct parisc_device *sba_dev = parisc_parent(pci_hba);
+ struct sba_device *sba = sba_dev->dev.driver_data;
+ char t = sba_dev->id.hw_type;
int iocnum = (pci_hba->hw_path >> 3); /* rope # */
- if ((t!=HPHW_IOA) && (t!=HPHW_BCPORT))
- BUG();
+ WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
return &(sba->ioc[iocnum]);
}
+
+
+/**
+ * sba_directed_lmmio - return first directed LMMIO range routed to rope
+ * @pa_dev: The parisc device.
+ * @r: resource PCI host controller wants start/end fields assigned.
+ *
+ * For the given parisc PCI controller, determine if any direct ranges
+ * are routed down the corresponding rope.
+ */
+void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
+{
+ struct parisc_device *sba_dev = parisc_parent(pci_hba);
+ struct sba_device *sba = sba_dev->dev.driver_data;
+ char t = sba_dev->id.hw_type;
+ int i;
+ int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
+
+ BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
+
+ r->start = r->end = 0;
+
+ /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
+ for (i=0; i<4; i++) {
+ int base, size;
+ void __iomem *reg = sba->sba_hpa + i*0x18;
+
+ base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
+ if ((base & 1) == 0)
+ continue; /* not enabled */
+
+ size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
+
+ if ((size & (ROPES_PER_IOC-1)) != rope)
+ continue; /* directed down different rope */
+
+ r->start = (base & ~1UL) | PCI_F_EXTEND;
+ size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
+ r->end = r->start + size;
+ }
+}
+
+
+/**
+ * sba_distributed_lmmio - return portion of distributed LMMIO range
+ * @pa_dev: The parisc device.
+ * @r: resource PCI host controller wants start/end fields assigned.
+ *
+ * For the given parisc PCI controller, return portion of distributed LMMIO
+ * range. The distributed LMMIO is always present and it's just a question
+ * of the base address and size of the range.
+ */
+void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
+{
+ struct parisc_device *sba_dev = parisc_parent(pci_hba);
+ struct sba_device *sba = sba_dev->dev.driver_data;
+ char t = sba_dev->id.hw_type;
+ int base, size;
+ int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
+
+ BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
+
+ r->start = r->end = 0;
+
+ base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
+ if ((base & 1) == 0) {
+ BUG(); /* Gah! Distr Range wasn't enabled! */
+ return;
+ }
+
+ r->start = (base & ~1UL) | PCI_F_EXTEND;
+
+ size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
+ r->start += rope * (size + 1); /* adjust base for this rope */
+ r->end = r->start + size;
+}