{
u16 pci_cmd, pci_bctl;
struct pci_dev *cdev;
- struct hotplug_params hpp;
+ struct hotplug_params hpp = {0x8, 0x40, 0, 0}; /* defaults */
/* Program hpp values for this device */
if (!(dev->hdr_type == PCI_HEADER_TYPE_NORMAL ||
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
return;
- /* use default values if we can't get them from firmware */
- if (get_hp_params_from_firmware(dev, &hpp)) {
- hpp.cache_line_size = 8;
- hpp.latency_timer = 0x40;
- hpp.enable_serr = 0;
- hpp.enable_perr = 0;
- }
+ get_hp_params_from_firmware(dev, &hpp);
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp.cache_line_size);
pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp.latency_timer);