/* Mandatory power management transition delays */
/* see PCI PM 1.1 5.6.1 table 18 */
if(state == 3 || dev->current_state == 3)
- {
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ/100);
- }
+ msleep(10);
else if(state == 2 || dev->current_state == 2)
udelay(200);
dev->current_state = state;
int
pci_enable_device(struct pci_dev *dev)
{
+ dev->is_enabled = 1;
return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
}
pci_disable_device(struct pci_dev *dev)
{
u16 pci_command;
+
+ dev->is_enabled = 0;
+ dev->is_busmaster = 0;
pci_read_config_word(dev, PCI_COMMAND, &pci_command);
if (pci_command & PCI_COMMAND_MASTER) {
pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
value &= PCI_PM_CAP_PME_MASK;
- value >>= ffs(value); /* First bit of mask */
+ value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
/* Check if it can generate PME# from requested state. */
if (!value || !(value & (1 << state)))
cmd |= PCI_COMMAND_MASTER;
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
+ dev->is_busmaster = 1;
pcibios_set_master(dev);
}
if (cacheline_size == pci_cache_line_size)
return 0;
- printk(KERN_WARNING "PCI: cache line size of %d is not supported "
+ printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
"by device %s\n", pci_cache_line_size << 2, pci_name(dev));
return -EINVAL;
struct pci_dev *dev = NULL;
while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
- pci_fixup_device(PCI_FIXUP_FINAL, dev);
+ pci_fixup_device(pci_fixup_final, dev);
}
return 0;
}