#include "ioasm.h"
#include "chsc.h"
-#define VERSION_QDIO_C "$Revision: 1.86 $"
+#define VERSION_QDIO_C "$Revision: 1.93 $"
/****************** MODULE PARAMETER VARIABLES ********************/
MODULE_AUTHOR("Utz Bacher <utz.bacher@de.ibm.com>");
sprintf(dbf_text,"%4x%2x%2x",q->irq,q->q_no,
atomic_read(&q->busy_siga_counter));
QDIO_DBF_TEXT3(0,trace,dbf_text);
- q->timing.busy_start=0;
#endif /* CONFIG_QDIO_DEBUG */
+ q->timing.busy_start=0;
break;
case (2|QDIO_SIGA_ERROR_B_BIT_SET):
/* cc=2 and busy bit: */
#endif /* QDIO_USE_PROCESSING_STATE */
/*
* not needed, as the inbound queue will be synced on the next
- * siga-r
+ * siga-r, resp. tiqdio_is_inbound_q_done will do the siga-s
*/
/*SYNC_MEMORY;*/
f++;
/* means, no more buffers to be filled */
inline static int
-iqdio_is_inbound_q_done(struct qdio_q *q)
+tiqdio_is_inbound_q_done(struct qdio_q *q)
{
int no_used;
#ifdef CONFIG_QDIO_DEBUG
goto out;
qdio_kick_inbound_handler(q);
- if (iqdio_is_inbound_q_done(q))
+ if (tiqdio_is_inbound_q_done(q))
if (!qdio_stop_polling(q)) {
/*
* we set the flags to get into the stuff next time,
u32 kc:4;
u32 reserved4:21;
u32 isc:3;
- u32 reserved5[2];
+ u32 word_with_d_bit;
+ /* set to 0x10000000 to enable
+ * time delay disablement facility */
+ u32 reserved5;
u32 subsystem_id;
u32 reserved6[1004];
struct chsc_header response;
scssc_area->kc = QDIO_STORAGE_KEY;
scssc_area->isc = TIQDIO_THININT_ISC;
scssc_area->subsystem_id = (1<<16) + irq_ptr->irq;
+ /* enables the time delay disablement facility. Don't care
+ * whether it is really there (i.e. we haven't checked for
+ * it) */
+ scssc_area->word_with_d_bit = 0x10000000;
+
+
result = chsc(scssc_area);
if (result) {
init_MUTEX(&irq_ptr->setting_up_sema);
+ /* QDR must be in DMA area since CCW data address is only 32 bit */
irq_ptr->qdr=kmalloc(sizeof(struct qdr), GFP_KERNEL | GFP_DMA);
if (!(irq_ptr->qdr)) {
kfree(irq_ptr);