#include <linux/libata.h>
#define DRV_NAME "ata_piix"
-#define DRV_VERSION "1.02"
+#define DRV_VERSION "1.03"
enum {
PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
ICH5_PMR = 0x90, /* port mapping register */
ICH5_PCS = 0x92, /* port control and status */
+ PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
ich5_pata = 0,
ich5_sata = 1,
piix4_pata = 2,
+ ich6_sata = 3,
+ ich6_sata_rm = 4,
+ ich7_sata = 5,
};
static int piix_init_one (struct pci_dev *pdev,
static void piix_pata_phy_reset(struct ata_port *ap);
static void piix_sata_phy_reset(struct ata_port *ap);
-static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev,
- unsigned int pio);
-static void piix_set_udmamode (struct ata_port *ap, struct ata_device *adev,
- unsigned int udma);
+static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
+static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
static unsigned int in_module_init = 1;
{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
-
- /* ICH6 operates in two modes, "looks-like-ICH5" mode,
- * and enhanced mode, with queueing and other fancy stuff.
- * This is distinguished by PCI class code.
- */
- { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID,
- PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich5_sata },
- { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID,
- PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich5_sata },
+ { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
+ { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
+ { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
+ { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
+ { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
{ } /* terminate list */
};
static Scsi_Host_Template piix_sht = {
.module = THIS_MODULE,
.name = DRV_NAME,
+ .ioctl = ata_scsi_ioctl,
.queuecommand = ata_scsi_queuecmd,
.eh_strategy_handler = ata_scsi_error,
.can_queue = ATA_DEF_QUEUE,
static struct ata_port_operations piix_pata_ops = {
.port_disable = ata_port_disable,
.set_piomode = piix_set_piomode,
- .set_udmamode = piix_set_udmamode,
+ .set_dmamode = piix_set_dmamode,
- .tf_load = ata_tf_load_pio,
- .tf_read = ata_tf_read_pio,
- .check_status = ata_check_status_pio,
- .exec_command = ata_exec_command_pio,
+ .tf_load = ata_tf_load,
+ .tf_read = ata_tf_read,
+ .check_status = ata_check_status,
+ .exec_command = ata_exec_command,
+ .dev_select = ata_std_dev_select,
.phy_reset = piix_pata_phy_reset,
- .bmdma_setup = ata_bmdma_setup_pio,
- .bmdma_start = ata_bmdma_start_pio,
- .fill_sg = ata_fill_sg,
+ .bmdma_setup = ata_bmdma_setup,
+ .bmdma_start = ata_bmdma_start,
+ .bmdma_stop = ata_bmdma_stop,
+ .bmdma_status = ata_bmdma_status,
+ .qc_prep = ata_qc_prep,
+ .qc_issue = ata_qc_issue_prot,
+
.eng_timeout = ata_eng_timeout,
.irq_handler = ata_interrupt,
+ .irq_clear = ata_bmdma_irq_clear,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
static struct ata_port_operations piix_sata_ops = {
.port_disable = ata_port_disable,
- .set_piomode = piix_set_piomode,
- .set_udmamode = piix_set_udmamode,
- .tf_load = ata_tf_load_pio,
- .tf_read = ata_tf_read_pio,
- .check_status = ata_check_status_pio,
- .exec_command = ata_exec_command_pio,
+ .tf_load = ata_tf_load,
+ .tf_read = ata_tf_read,
+ .check_status = ata_check_status,
+ .exec_command = ata_exec_command,
+ .dev_select = ata_std_dev_select,
.phy_reset = piix_sata_phy_reset,
- .bmdma_setup = ata_bmdma_setup_pio,
- .bmdma_start = ata_bmdma_start_pio,
- .fill_sg = ata_fill_sg,
+ .bmdma_setup = ata_bmdma_setup,
+ .bmdma_start = ata_bmdma_start,
+ .bmdma_stop = ata_bmdma_stop,
+ .bmdma_status = ata_bmdma_status,
+ .qc_prep = ata_qc_prep,
+ .qc_issue = ata_qc_issue_prot,
+
.eng_timeout = ata_eng_timeout,
.irq_handler = ata_interrupt,
+ .irq_clear = ata_bmdma_irq_clear,
.port_start = ata_port_start,
.port_stop = ata_port_stop,
.sht = &piix_sht,
.host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
PIIX_FLAG_CHECKINTR,
- .pio_mask = 0x03, /* pio3-4 */
- .udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */
+ .pio_mask = 0x1f, /* pio0-4 */
+#if 0
+ .mwdma_mask = 0x06, /* mwdma1-2 */
+#else
+ .mwdma_mask = 0x00, /* mwdma broken */
+#endif
+ .udma_mask = 0x3f, /* udma0-5 */
.port_ops = &piix_pata_ops,
},
.sht = &piix_sht,
.host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
- .pio_mask = 0x03, /* pio3-4 */
- .udma_mask = 0x7f, /* udma0-6 ; FIXME */
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = 0x7f, /* udma0-6 */
.port_ops = &piix_sata_ops,
},
{
.sht = &piix_sht,
.host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
- .pio_mask = 0x03, /* pio3-4 */
- .udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */
+ .pio_mask = 0x1f, /* pio0-4 */
+#if 0
+ .mwdma_mask = 0x06, /* mwdma1-2 */
+#else
+ .mwdma_mask = 0x00, /* mwdma broken */
+#endif
+ .udma_mask = ATA_UDMA_MASK_40C,
.port_ops = &piix_pata_ops,
},
+
+ /* ich6_sata */
+ {
+ .sht = &piix_sht,
+ .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
+ PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
+ ATA_FLAG_SLAVE_POSS,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = 0x7f, /* udma0-6 */
+ .port_ops = &piix_sata_ops,
+ },
+
+ /* ich6_sata_rm */
+ {
+ .sht = &piix_sht,
+ .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
+ PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
+ ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = 0x7f, /* udma0-6 */
+ .port_ops = &piix_sata_ops,
+ },
+
+ /* ich7_sata */
+ {
+ .sht = &piix_sht,
+ .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
+ PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
+ ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
+ .pio_mask = 0x1f, /* pio0-4 */
+ .mwdma_mask = 0x07, /* mwdma0-2 */
+ .udma_mask = 0x7f, /* udma0-6 */
+ .port_ops = &piix_sata_ops,
+ },
};
static struct pci_bits piix_enable_bits[] = {
MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
+MODULE_VERSION(DRV_VERSION);
/**
* piix_pata_cbl_detect - Probe host controller cable detect info
* @ap: Port for which cable detect info is desired
*
- * Read 80c cable indicator from SATA PCI device's PCI config
+ * Read 80c cable indicator from ATA PCI device's PCI config
* register. This register is normally set by firmware (BIOS).
*
* LOCKING:
*/
static void piix_pata_cbl_detect(struct ata_port *ap)
{
- struct pci_dev *pdev = ap->host_set->pdev;
+ struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
u8 tmp, mask;
/* no 80c support in host controller? */
goto cbl40;
/* check BIOS cable detect results */
- mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
+ mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
if ((tmp & mask) == 0)
goto cbl40;
static void piix_pata_phy_reset(struct ata_port *ap)
{
- if (!pci_test_config_bits(ap->host_set->pdev,
- &piix_enable_bits[ap->port_no])) {
+ struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
+
+ if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
ata_port_disable(ap);
printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
return;
*/
static int piix_sata_probe (struct ata_port *ap)
{
- struct pci_dev *pdev = ap->host_set->pdev;
+ struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
int orig_mask, mask, i;
u8 pcs;
- mask = (PIIX_PORT_PRESENT << ap->port_no) |
- (PIIX_PORT_ENABLED << ap->port_no);
+ mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
+ (PIIX_PORT_ENABLED << ap->hard_port_no);
pci_read_config_byte(pdev, ICH5_PCS, &pcs);
orig_mask = (int) pcs & 0xff;
mask = (PIIX_PORT_PRESENT << i) | (PIIX_PORT_ENABLED << i);
if ((orig_mask & mask) == mask)
- if (combined || (i == ap->port_no))
+ if (combined || (i == ap->hard_port_no))
return 1;
}
static void piix_sata_phy_reset(struct ata_port *ap)
{
- if (!pci_test_config_bits(ap->host_set->pdev,
- &piix_enable_bits[ap->port_no])) {
- ata_port_disable(ap);
- printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
- return;
- }
-
if (!piix_sata_probe(ap)) {
ata_port_disable(ap);
printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
* None (inherited from caller).
*/
-static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev,
- unsigned int pio)
+static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
- struct pci_dev *dev = ap->host_set->pdev;
- unsigned int is_slave = (adev->flags & ATA_DFLAG_MASTER) ? 0 : 1;
- unsigned int master_port= ap->port_no ? 0x42 : 0x40;
+ unsigned int pio = adev->pio_mode - XFER_PIO_0;
+ struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
+ unsigned int is_slave = (adev->devno != 0);
+ unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
unsigned int slave_port = 0x44;
u16 master_data;
u8 slave_data;
/* enable PPE, IE and TIME */
master_data |= 0x0070;
pci_read_config_byte(dev, slave_port, &slave_data);
- slave_data &= (ap->port_no ? 0x0f : 0xf0);
+ slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
slave_data |=
(timings[pio][0] << 2) |
- (timings[pio][1] << (ap->port_no ? 4 : 0));
+ (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
} else {
master_data &= 0xccf8;
/* enable PPE, IE and TIME */
}
/**
- * piix_set_udmamode - Initialize host controller PATA PIO timings
+ * piix_set_dmamode - Initialize host controller PATA PIO timings
* @ap: Port whose timings we are configuring
* @adev: um
* @udma: udma mode, 0 - 6
* None (inherited from caller).
*/
-static void piix_set_udmamode (struct ata_port *ap, struct ata_device *adev,
- unsigned int udma)
+static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
- struct pci_dev *dev = ap->host_set->pdev;
- u8 maslave = ap->port_no ? 0x42 : 0x40;
+ unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
+ struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
+ u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
u8 speed = udma;
- unsigned int drive_dn = (ap->port_no ? 2 : 0) + adev->devno;
+ unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
int a_speed = 3 << (drive_dn * 4);
int u_flag = 1 << drive_dn;
int v_flag = 0x01 << drive_dn;
case XFER_UDMA_3:
case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
+ case XFER_MW_DMA_2:
+ case XFER_MW_DMA_1: break;
default:
BUG();
return;
}
- if (!(reg48 & u_flag))
- pci_write_config_byte(dev, 0x48, reg48 | u_flag);
- if (speed == XFER_UDMA_5) {
- pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
+ if (speed >= XFER_UDMA_0) {
+ if (!(reg48 & u_flag))
+ pci_write_config_byte(dev, 0x48, reg48 | u_flag);
+ if (speed == XFER_UDMA_5) {
+ pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
+ } else {
+ pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
+ }
+ if ((reg4a & a_speed) != u_speed)
+ pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
+ if (speed > XFER_UDMA_2) {
+ if (!(reg54 & v_flag))
+ pci_write_config_byte(dev, 0x54, reg54 | v_flag);
+ } else
+ pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
} else {
- pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
+ if (reg48 & u_flag)
+ pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
+ if (reg4a & a_speed)
+ pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
+ if (reg54 & v_flag)
+ pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
+ if (reg55 & w_flag)
+ pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
}
- if ((reg4a & a_speed) != u_speed)
- pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
- if (speed > XFER_UDMA_2) {
- if (!(reg54 & v_flag))
- pci_write_config_byte(dev, 0x54, reg54 | v_flag);
- } else
- pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
}
/* move to PCI layer, integrate w/ MSI stuff */
}
}
+#define AHCI_PCI_BAR 5
+#define AHCI_GLOBAL_CTL 0x04
+#define AHCI_ENABLE (1 << 31)
+static int piix_disable_ahci(struct pci_dev *pdev)
+{
+ void *mmio;
+ unsigned long addr;
+ u32 tmp;
+ int rc = 0;
+
+ /* BUG: pci_enable_device has not yet been called. This
+ * works because this device is usually set up by BIOS.
+ */
+
+ addr = pci_resource_start(pdev, AHCI_PCI_BAR);
+ if (!addr || !pci_resource_len(pdev, AHCI_PCI_BAR))
+ return 0;
+
+ mmio = ioremap(addr, 64);
+ if (!mmio)
+ return -ENOMEM;
+
+ tmp = readl(mmio + AHCI_GLOBAL_CTL);
+ if (tmp & AHCI_ENABLE) {
+ tmp &= ~AHCI_ENABLE;
+ writel(tmp, mmio + AHCI_GLOBAL_CTL);
+
+ tmp = readl(mmio + AHCI_GLOBAL_CTL);
+ if (tmp & AHCI_ENABLE)
+ rc = -EIO;
+ }
+
+ iounmap(mmio);
+ return rc;
+}
+
/**
* piix_init_one - Register PIIX ATA PCI device with kernel services
* @pdev: PCI device to register
port_info[0] = &piix_port_info[ent->driver_data];
port_info[1] = NULL;
+ if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
+ int rc = piix_disable_ahci(pdev);
+ if (rc)
+ return rc;
+ }
+
if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
u8 tmp;
pci_read_config_byte(pdev, ICH5_PMR, &tmp);
git://git.onelab.eu / linux-2.6.git / blobdiff