#include "megaraid_ioctl.h"
-#define MEGARAID_VERSION "2.20.4.0"
-#define MEGARAID_EXT_VERSION "(Release Date: Mon Sep 27 22:15:07 EDT 2004)"
+#define MEGARAID_VERSION "2.20.4.7"
+#define MEGARAID_EXT_VERSION "(Release Date: Mon Nov 14 12:27:22 EST 2005)"
/*
#define PCI_DEVICE_ID_PERC4_DC 0x1960
#define PCI_SUBSYS_ID_PERC4_DC 0x0518
-#define PCI_DEVICE_ID_PERC4_QC 0x0407
-#define PCI_SUBSYS_ID_PERC4_QC 0x0531
+#define PCI_DEVICE_ID_VERDE 0x0407
#define PCI_DEVICE_ID_PERC4_DI_EVERGLADES 0x000F
#define PCI_SUBSYS_ID_PERC4_DI_EVERGLADES 0x014A
#define PCI_DEVICE_ID_PERC4E_DI_GUADALUPE 0x0013
#define PCI_SUBSYS_ID_PERC4E_DI_GUADALUPE 0x0170
-#define PCI_DEVICE_ID_PERC4E_DC_320_2E 0x0408
-#define PCI_SUBSYS_ID_PERC4E_DC_320_2E 0x0002
-
-#define PCI_DEVICE_ID_PERC4E_SC_320_1E 0x0408
-#define PCI_SUBSYS_ID_PERC4E_SC_320_1E 0x0001
+#define PCI_DEVICE_ID_DOBSON 0x0408
#define PCI_DEVICE_ID_MEGARAID_SCSI_320_0 0x1960
#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_0 0xA520
#define PCI_DEVICE_ID_MEGARAID_SCSI_320_2 0x1960
#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2 0x0518
-#define PCI_DEVICE_ID_MEGARAID_SCSI_320_0x 0x0407
-#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_0x 0x0530
-
-#define PCI_DEVICE_ID_MEGARAID_SCSI_320_2x 0x0407
-#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2x 0x0532
-
-#define PCI_DEVICE_ID_MEGARAID_SCSI_320_4x 0x0407
-#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_4x 0x0531
-
-#define PCI_DEVICE_ID_MEGARAID_SCSI_320_1E 0x0408
-#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_1E 0x0001
-
-#define PCI_DEVICE_ID_MEGARAID_SCSI_320_2E 0x0408
-#define PCI_SUBSYS_ID_MEGARAID_SCSI_320_2E 0x0002
-
#define PCI_DEVICE_ID_MEGARAID_I4_133_RAID 0x1960
#define PCI_SUBSYS_ID_MEGARAID_I4_133_RAID 0x0522
#define PCI_DEVICE_ID_MEGARAID_SATA_150_6 0x1960
#define PCI_SUBSYS_ID_MEGARAID_SATA_150_6 0x0523
-#define PCI_DEVICE_ID_MEGARAID_SATA_300_4x 0x0409
-#define PCI_SUBSYS_ID_MEGARAID_SATA_300_4x 0x3004
-
-#define PCI_DEVICE_ID_MEGARAID_SATA_300_8x 0x0409
-#define PCI_SUBSYS_ID_MEGARAID_SATA_300_8x 0x3008
-
-#define PCI_DEVICE_ID_INTEL_RAID_SRCU42X 0x0407
-#define PCI_SUBSYS_ID_INTEL_RAID_SRCU42X 0x0532
+#define PCI_DEVICE_ID_LINDSAY 0x0409
#define PCI_DEVICE_ID_INTEL_RAID_SRCS16 0x1960
#define PCI_SUBSYS_ID_INTEL_RAID_SRCS16 0x0523
-#define PCI_DEVICE_ID_INTEL_RAID_SRCU42E 0x0408
-#define PCI_SUBSYS_ID_INTEL_RAID_SRCU42E 0x0002
-
-#define PCI_DEVICE_ID_INTEL_RAID_SRCZCRX 0x0407
-#define PCI_SUBSYS_ID_INTEL_RAID_SRCZCRX 0x0530
-
-#define PCI_DEVICE_ID_INTEL_RAID_SRCS28X 0x0409
-#define PCI_SUBSYS_ID_INTEL_RAID_SRCS28X 0x3008
-
-#define PCI_DEVICE_ID_INTEL_RAID_SROMBU42E_ALIEF 0x0408
-#define PCI_SUBSYS_ID_INTEL_RAID_SROMBU42E_ALIEF 0x3431
-
-#define PCI_DEVICE_ID_INTEL_RAID_SROMBU42E_HARWICH 0x0408
-#define PCI_SUBSYS_ID_INTEL_RAID_SROMBU42E_HARWICH 0x3499
-
#define PCI_DEVICE_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x1960
#define PCI_SUBSYS_ID_INTEL_RAID_SRCU41L_LAKE_SHETEK 0x0520
-#define PCI_DEVICE_ID_FSC_MEGARAID_PCI_EXPRESS_ROMB 0x0408
-#define PCI_SUBSYS_ID_FSC_MEGARAID_PCI_EXPRESS_ROMB 0x1065
-
-#define PCI_DEVICE_ID_MEGARAID_ACER_ROMB_2E 0x0408
-#define PCI_SUBSYS_ID_MEGARAID_ACER_ROMB_2E 0x004D
-
#define PCI_SUBSYS_ID_PERC3_QC 0x0471
#define PCI_SUBSYS_ID_PERC3_DC 0x0493
#define PCI_SUBSYS_ID_PERC3_SC 0x0475
-#ifndef PCI_SUBSYS_ID_FSC
-#define PCI_SUBSYS_ID_FSC 0x1734
-#endif
#define MBOX_MAX_SCSI_CMDS 128 // number of cmds reserved for kernel
#define MBOX_MAX_USER_CMDS 32 // number of cmds for applications
* @param hw_error : set if FW not responding
* @param fast_load : If set, skip physical device scanning
* @channel_class : channel class, RAID or SCSI
+ * @sysfs_sem : semaphore to serialize access to sysfs res.
+ * @sysfs_uioc : management packet to issue FW calls from sysfs
+ * @sysfs_mbox64 : mailbox packet to issue FW calls from sysfs
+ * @sysfs_buffer : data buffer for FW commands issued from sysfs
+ * @sysfs_buffer_dma : DMA buffer for FW commands issued from sysfs
+ * @sysfs_wait_q : wait queue for sysfs operations
+ * @random_del_supported : set if the random deletion is supported
+ * @curr_ldmap : current LDID map
*
* Initialization structure for mailbox controllers: memory based and IO based
* All the fields in this structure are LLD specific and may be discovered at
*
* NOTE: The fields of this structures are placed to minimize cache misses
*/
+#define MAX_LD_EXTENDED64 64
typedef struct {
mbox64_t *una_mbox64;
dma_addr_t una_mbox64_dma;
dma_addr_t mbox_dma;
spinlock_t mailbox_lock;
unsigned long baseport;
- unsigned long baseaddr;
+ void __iomem * baseaddr;
struct mraid_pci_blk mbox_pool[MBOX_MAX_SCSI_CMDS];
struct dma_pool *mbox_pool_handle;
struct mraid_pci_blk epthru_pool[MBOX_MAX_SCSI_CMDS];
int hw_error;
int fast_load;
uint8_t channel_class;
+ struct semaphore sysfs_sem;
+ uioc_t *sysfs_uioc;
+ mbox64_t *sysfs_mbox64;
+ caddr_t sysfs_buffer;
+ dma_addr_t sysfs_buffer_dma;
+ wait_queue_head_t sysfs_wait_q;
+ int random_del_supported;
+ uint16_t curr_ldmap[MAX_LD_EXTENDED64];
} mraid_device_t;
// route to raid device from adapter