#include <linux/delay.h>
#include <linux/blkdev.h>
#include <linux/stat.h>
+#include <linux/delay.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include "scsi.h"
-#include "hosts.h"
+#include <scsi/scsi_dbg.h>
+#include <scsi/scsi_host.h>
#include "seagate.h"
#include <scsi/scsi_ioctl.h>
calculate memory mapped register
location. */
-static unsigned long st0x_cr_sr; /* control register write, status
+static void __iomem *st0x_cr_sr; /* control register write, status
register read. 256 bytes in
length.
Read is status of SCSI BUS, as per
STAT masks. */
-static unsigned long st0x_dr; /* data register, read write 256
+static void __iomem *st0x_dr; /* data register, read write 256
bytes in length. */
static volatile int st0x_aborted = 0; /* set when we are aborted, ie by a
boards */
static int irq = IRQ;
-MODULE_PARM (base_address, "i");
-MODULE_PARM (controller_type, "b");
-MODULE_PARM (irq, "i");
+module_param(base_address, uint, 0);
+module_param(controller_type, byte, 0);
+module_param(irq, int, 0);
MODULE_LICENSE("GPL");
#define retcode(result) (((result) << 16) | (message << 8) | status)
-#define STATUS ((u8) isa_readb(st0x_cr_sr))
-#define DATA ((u8) isa_readb(st0x_dr))
-#define WRITE_CONTROL(d) { isa_writeb((d), st0x_cr_sr); }
-#define WRITE_DATA(d) { isa_writeb((d), st0x_dr); }
+#define STATUS ((u8) readb(st0x_cr_sr))
+#define DATA ((u8) readb(st0x_dr))
+#define WRITE_CONTROL(d) { writeb((d), st0x_cr_sr); }
+#define WRITE_DATA(d) { writeb((d), st0x_dr); }
#ifndef OVERRIDE
static unsigned int seagate_bases[] = {
#define ULOOP( i ) for (clock = i*8;;)
#define TIMEOUT (!(clock--))
-int __init seagate_st0x_detect (Scsi_Host_Template * tpnt)
+int __init seagate_st0x_detect (struct scsi_host_template * tpnt)
{
struct Scsi_Host *instance;
int i, j;
+ unsigned long cr, dr;
tpnt->proc_name = "seagate";
/*
* space for the on-board RAM instead.
*/
- for (i = 0; i < (sizeof (seagate_bases) / sizeof (unsigned int)); ++i)
- for (j = 0; !base_address && j < NUM_SIGNATURES; ++j)
- if (isa_check_signature(seagate_bases[i] + signatures[j].offset, signatures[j].signature, signatures[j].length)) {
+ for (i = 0; i < (sizeof (seagate_bases) / sizeof (unsigned int)); ++i) {
+ void __iomem *p = ioremap(seagate_bases[i], 0x2000);
+ if (!p)
+ continue;
+ for (j = 0; j < NUM_SIGNATURES; ++j)
+ if (check_signature(p + signatures[j].offset, signatures[j].signature, signatures[j].length)) {
base_address = seagate_bases[i];
controller_type = signatures[j].type;
+ break;
}
+ iounmap(p);
+ }
#endif /* OVERRIDE */
}
/* (! controller_type) */
return 0;
}
- st0x_cr_sr = base_address + (controller_type == SEAGATE ? 0x1a00 : 0x1c00);
- st0x_dr = st0x_cr_sr + 0x200;
+ cr = base_address + (controller_type == SEAGATE ? 0x1a00 : 0x1c00);
+ dr = cr + 0x200;
+ st0x_cr_sr = ioremap(cr, 0x100);
+ st0x_dr = ioremap(dr, 0x100);
DANY("%s detected. Base address = %x, cr = %x, dr = %x\n",
- tpnt->name, base_address, st0x_cr_sr, st0x_dr);
+ tpnt->name, base_address, cr, dr);
/*
* At all times, we will use IRQ 5. Should also check for IRQ3
#if (DEBUG & PRINT_COMMAND)
printk("scsi%d : target = %d, command = ", hostno, target);
- print_command((unsigned char *) cmnd);
+ __scsi_print_command((unsigned char *) cmnd);
#endif
#if (DEBUG & PHASE_RESELECT)
#endif
"loop 1b;"
/* output */ :
- /* input */ :"D" (phys_to_virt (st0x_dr)),
+ /* input */ :"D" (st0x_dr),
"S"
(data),
"c" (SCint->transfersize)
: "eax", "ecx",
"esi");
#else /* SEAGATE_USE_ASM */
- {
-#ifdef FAST32
- unsigned int *iop = phys_to_virt (st0x_dr);
- const unsigned int *dp =(unsigned int *) data;
- int xferlen = transfersize >> 2;
-#else
- unsigned char *iop = phys_to_virt (st0x_dr);
- const unsigned char *dp = data;
- int xferlen = transfersize;
-#endif
- for (; xferlen; --xferlen)
- *iop = *dp++;
- }
+ memcpy_toio(st0x_dr, data, transfersize);
#endif /* SEAGATE_USE_ASM */
/* SJT: End */
len -= transfersize;
"=D" (__dummy_2)
/* input */
: "0" (data), "1" (len),
- "2" (phys_to_virt
- (st0x_cr_sr)),
- "3" (phys_to_virt
- (st0x_dr))
+ "2" (st0x_cr_sr),
+ "3" (st0x_dr)
/* clobbered */
: "eax");
#else /* SEAGATE_USE_ASM */
#endif
"loop 1b\n\t"
/* output */ :
- /* input */ :"S" (phys_to_virt (st0x_dr)),
+ /* input */ :"S" (st0x_dr),
"D"
(data),
"c" (SCint->transfersize)
: "eax", "ecx",
"edi");
#else /* SEAGATE_USE_ASM */
- {
-#ifdef FAST32
- const unsigned int *iop =
- phys_to_virt (st0x_dr);
- unsigned int *dp =
- (unsigned int *) data;
- int xferlen = len >> 2;
-#else
- const unsigned char *iop =
- phys_to_virt (st0x_dr);
- unsigned char *dp = data;
- int xferlen = len;
-#endif
- for (; xferlen; --xferlen)
- *dp++ = *iop;
- }
+ memcpy_fromio(data, st0x_dr, len);
#endif /* SEAGATE_USE_ASM */
/* SJT: End */
len -= transfersize;
"=b" (__dummy_4)
/* input */
: "0" (data), "1" (len),
- "2" (phys_to_virt
- (st0x_cr_sr)),
- "3" (phys_to_virt
- (st0x_dr))
+ "2" (st0x_cr_sr),
+ "3" (st0x_dr)
/* clobbered */
: "eax");
#else /* SEAGATE_USE_ASM */
printk("\n");
#endif
printk("scsi%d : status = ", hostno);
- print_status(status);
+ scsi_print_status(status);
printk(" message = %02x\n", message);
#endif
/* assert RESET signal on SCSI bus. */
WRITE_CONTROL (BASE_CMD | CMD_RST);
- udelay (20 * 1000);
+ mdelay (20);
WRITE_CONTROL (BASE_CMD);
st0x_aborted = DID_RESET;
return SUCCESS;
}
-static int seagate_st0x_host_reset(Scsi_Cmnd *SCpnt)
-{
- return FAILED;
-}
-
-static int seagate_st0x_device_reset(Scsi_Cmnd *SCpnt)
-{
- return FAILED;
-}
-
static int seagate_st0x_release(struct Scsi_Host *shost)
{
if (shost->irq)
return 0;
}
-static Scsi_Host_Template driver_template = {
+static struct scsi_host_template driver_template = {
.detect = seagate_st0x_detect,
.release = seagate_st0x_release,
.info = seagate_st0x_info,
.queuecommand = seagate_st0x_queue_command,
.eh_abort_handler = seagate_st0x_abort,
.eh_bus_reset_handler = seagate_st0x_bus_reset,
- .eh_host_reset_handler = seagate_st0x_host_reset,
- .eh_device_reset_handler = seagate_st0x_device_reset,
.can_queue = 1,
.this_id = 7,
.sg_tablesize = SG_ALL,
git://git.onelab.eu / linux-2.6.git / blobdiff