/*
* Copyright (c) 2001 by David Brownell
- *
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* - data used only by the HCD ... kmalloc is fine
* - async and periodic schedules, shared by HC and HCD ... these
* need to use dma_pool or dma_alloc_coherent
- * - driver buffers, read/written by HC ... single shot DMA mapped
+ * - driver buffers, read/written by HC ... single shot DMA mapped
*
* There's also PCI "register" data, which is memory mapped.
* No memory seen by this driver is pageable.
*/
-/*-------------------------------------------------------------------------*/
-/*
- * Allocator / cleanup for the per device structure
- * Called by hcd init / removal code
- */
-static struct usb_hcd *ehci_hcd_alloc (void)
-{
- struct ehci_hcd *ehci;
-
- ehci = (struct ehci_hcd *)
- kmalloc (sizeof (struct ehci_hcd), GFP_KERNEL);
- if (ehci != 0) {
- memset (ehci, 0, sizeof (struct ehci_hcd));
- ehci->hcd.product_desc = "EHCI Host Controller";
- return &ehci->hcd;
- }
- return 0;
-}
-
-static void ehci_hcd_free (struct usb_hcd *hcd)
-{
- kfree (hcd_to_ehci (hcd));
-}
-
/*-------------------------------------------------------------------------*/
/* Allocate the key transfer structures from the previously allocated pool */
INIT_LIST_HEAD (&qtd->qtd_list);
}
-static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, int flags)
+static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
{
struct ehci_qtd *qtd;
dma_addr_t dma;
qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
- if (qtd != 0) {
+ if (qtd != NULL) {
ehci_qtd_init (qtd, dma);
}
return qtd;
}
if (qh->dummy)
ehci_qtd_free (ehci, qh->dummy);
- usb_put_dev (qh->dev);
dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
}
-static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, int flags)
+static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
{
struct ehci_qh *qh;
dma_addr_t dma;
return qh;
memset (qh, 0, sizeof *qh);
- kref_init(&qh->kref, qh_destroy);
+ kref_init(&qh->kref);
qh->ehci = ehci;
qh->qh_dma = dma;
// INIT_LIST_HEAD (&qh->qh_list);
/* dummy td enables safe urb queuing */
qh->dummy = ehci_qtd_alloc (ehci, flags);
- if (qh->dummy == 0) {
+ if (qh->dummy == NULL) {
ehci_dbg (ehci, "no dummy td\n");
dma_pool_free (ehci->qh_pool, qh, qh->qh_dma);
- qh = 0;
+ qh = NULL;
}
return qh;
}
static inline void qh_put (struct ehci_qh *qh)
{
- kref_put(&qh->kref);
+ kref_put(&qh->kref, qh_destroy);
}
/*-------------------------------------------------------------------------*/
-/* The queue heads and transfer descriptors are managed from pools tied
+/* The queue heads and transfer descriptors are managed from pools tied
* to each of the "per device" structures.
* This is the initialisation and cleanup code.
*/
{
if (ehci->async)
qh_put (ehci->async);
- ehci->async = 0;
+ ehci->async = NULL;
/* DMA consistent memory and pools */
if (ehci->qtd_pool)
dma_pool_destroy (ehci->qtd_pool);
- ehci->qtd_pool = 0;
+ ehci->qtd_pool = NULL;
if (ehci->qh_pool) {
dma_pool_destroy (ehci->qh_pool);
- ehci->qh_pool = 0;
+ ehci->qh_pool = NULL;
}
if (ehci->itd_pool)
dma_pool_destroy (ehci->itd_pool);
- ehci->itd_pool = 0;
+ ehci->itd_pool = NULL;
if (ehci->sitd_pool)
dma_pool_destroy (ehci->sitd_pool);
- ehci->sitd_pool = 0;
+ ehci->sitd_pool = NULL;
if (ehci->periodic)
- dma_free_coherent (ehci->hcd.self.controller,
+ dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
ehci->periodic_size * sizeof (u32),
ehci->periodic, ehci->periodic_dma);
- ehci->periodic = 0;
+ ehci->periodic = NULL;
/* shadow periodic table */
- if (ehci->pshadow)
- kfree (ehci->pshadow);
- ehci->pshadow = 0;
+ kfree(ehci->pshadow);
+ ehci->pshadow = NULL;
}
/* remember to add cleanup code (above) if you add anything here */
-static int ehci_mem_init (struct ehci_hcd *ehci, int flags)
+static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
{
int i;
/* QTDs for control/bulk/intr transfers */
- ehci->qtd_pool = dma_pool_create ("ehci_qtd",
- ehci->hcd.self.controller,
+ ehci->qtd_pool = dma_pool_create ("ehci_qtd",
+ ehci_to_hcd(ehci)->self.controller,
sizeof (struct ehci_qtd),
32 /* byte alignment (for hw parts) */,
4096 /* can't cross 4K */);
}
/* QHs for control/bulk/intr transfers */
- ehci->qh_pool = dma_pool_create ("ehci_qh",
- ehci->hcd.self.controller,
+ ehci->qh_pool = dma_pool_create ("ehci_qh",
+ ehci_to_hcd(ehci)->self.controller,
sizeof (struct ehci_qh),
32 /* byte alignment (for hw parts) */,
4096 /* can't cross 4K */);
}
/* ITD for high speed ISO transfers */
- ehci->itd_pool = dma_pool_create ("ehci_itd",
- ehci->hcd.self.controller,
+ ehci->itd_pool = dma_pool_create ("ehci_itd",
+ ehci_to_hcd(ehci)->self.controller,
sizeof (struct ehci_itd),
32 /* byte alignment (for hw parts) */,
4096 /* can't cross 4K */);
}
/* SITD for full/low speed split ISO transfers */
- ehci->sitd_pool = dma_pool_create ("ehci_sitd",
- ehci->hcd.self.controller,
+ ehci->sitd_pool = dma_pool_create ("ehci_sitd",
+ ehci_to_hcd(ehci)->self.controller,
sizeof (struct ehci_sitd),
32 /* byte alignment (for hw parts) */,
4096 /* can't cross 4K */);
}
/* Hardware periodic table */
- ehci->periodic = (u32 *)
- dma_alloc_coherent (ehci->hcd.self.controller,
- ehci->periodic_size * sizeof (u32),
+ ehci->periodic = (__le32 *)
+ dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
+ ehci->periodic_size * sizeof(__le32),
&ehci->periodic_dma, 0);
- if (ehci->periodic == 0) {
+ if (ehci->periodic == NULL) {
goto fail;
}
for (i = 0; i < ehci->periodic_size; i++)
ehci->periodic [i] = EHCI_LIST_END;
/* software shadow of hardware table */
- ehci->pshadow = kmalloc (ehci->periodic_size * sizeof (void *), flags);
- if (ehci->pshadow == 0) {
- goto fail;
- }
- memset (ehci->pshadow, 0, ehci->periodic_size * sizeof (void *));
-
- return 0;
+ ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
+ if (ehci->pshadow != NULL)
+ return 0;
fail:
ehci_dbg (ehci, "couldn't init memory\n");