struct ohci_regs *regs = controller->regs;
u32 temp;
- temp = readl (®s->revision) & 0xff;
+ temp = ohci_readl (®s->revision) & 0xff;
ohci_dbg_sw (controller, next, size,
"OHCI %d.%d, %s legacy support registers\n",
0x03 & (temp >> 4), (temp & 0x0f),
(temp & 0x10) ? "with" : "NO");
- temp = readl (®s->control);
+ temp = ohci_readl (®s->control);
ohci_dbg_sw (controller, next, size,
"control 0x%03x%s%s%s HCFS=%s%s%s%s%s CBSR=%d\n",
temp,
temp & OHCI_CTRL_CBSR
);
- temp = readl (®s->cmdstatus);
+ temp = ohci_readl (®s->cmdstatus);
ohci_dbg_sw (controller, next, size,
"cmdstatus 0x%05x SOC=%d%s%s%s%s\n", temp,
(temp & OHCI_SOC) >> 16,
);
ohci_dump_intr_mask (controller, "intrstatus",
- readl (®s->intrstatus), next, size);
+ ohci_readl (®s->intrstatus), next, size);
ohci_dump_intr_mask (controller, "intrenable",
- readl (®s->intrenable), next, size);
+ ohci_readl (®s->intrenable), next, size);
// intrdisable always same as intrenable
maybe_print_eds (controller, "ed_periodcurrent",
- readl (®s->ed_periodcurrent), next, size);
+ ohci_readl (®s->ed_periodcurrent), next, size);
maybe_print_eds (controller, "ed_controlhead",
- readl (®s->ed_controlhead), next, size);
+ ohci_readl (®s->ed_controlhead), next, size);
maybe_print_eds (controller, "ed_controlcurrent",
- readl (®s->ed_controlcurrent), next, size);
+ ohci_readl (®s->ed_controlcurrent), next, size);
maybe_print_eds (controller, "ed_bulkhead",
- readl (®s->ed_bulkhead), next, size);
+ ohci_readl (®s->ed_bulkhead), next, size);
maybe_print_eds (controller, "ed_bulkcurrent",
- readl (®s->ed_bulkcurrent), next, size);
+ ohci_readl (®s->ed_bulkcurrent), next, size);
maybe_print_eds (controller, "donehead",
- readl (®s->donehead), next, size);
+ ohci_readl (®s->donehead), next, size);
}
#define dbg_port_sw(hc,num,value,next,size) \
ohci_dbg (controller, "OHCI controller state\n");
// dumps some of the state we know about
- ohci_dump_status (controller, NULL, 0);
+ ohci_dump_status (controller, NULL, NULL);
if (controller->hcca)
ohci_dbg (controller,
"hcca frame #%04x\n", OHCI_FRAME_NO(controller->hcca));
- ohci_dump_roothub (controller, 1, NULL, 0);
+ ohci_dump_roothub (controller, 1, NULL, NULL);
}
static const char data0 [] = "DATA0";
} else {
/* we've seen it and what's after */
temp = 0;
- ed = 0;
+ ed = NULL;
}
} while (ed);
"hcca frame 0x%04x\n", OHCI_FRAME_NO(ohci->hcca));
/* other registers mostly affect frame timings */
- rdata = readl (®s->fminterval);
+ rdata = ohci_readl (®s->fminterval);
temp = scnprintf (next, size,
"fmintvl 0x%08x %sFSMPS=0x%04x FI=0x%04x\n",
rdata, (rdata >> 31) ? " FIT" : "",
size -= temp;
next += temp;
- rdata = readl (®s->fmremaining);
+ rdata = ohci_readl (®s->fmremaining);
temp = scnprintf (next, size, "fmremaining 0x%08x %sFR=0x%04x\n",
rdata, (rdata >> 31) ? " FRT" : "",
rdata & 0x3fff);
size -= temp;
next += temp;
- rdata = readl (®s->periodicstart);
+ rdata = ohci_readl (®s->periodicstart);
temp = scnprintf (next, size, "periodicstart 0x%04x\n",
rdata & 0x3fff);
size -= temp;
next += temp;
- rdata = readl (®s->lsthresh);
+ rdata = ohci_readl (®s->lsthresh);
temp = scnprintf (next, size, "lsthresh 0x%04x\n",
rdata & 0x3fff);
size -= temp;