if (par->Architecture >= NV_ARCH_40) {
pll = NV_RD32(par->PMC, 0x4020);
- P = (pll >> 16) & 0x07;
+ P = (pll >> 16) & 0x03;
pll = NV_RD32(par->PMC, 0x4024);
M = pll & 0xFF;
N = (pll >> 8) & 0xFF;
- if (((par->Chipset & 0xfff0) == 0x0290) ||
- ((par->Chipset & 0xfff0) == 0x0390)) {
- MB = 1;
- NB = 1;
- } else {
- MB = (pll >> 16) & 0xFF;
- NB = (pll >> 24) & 0xFF;
- }
+ MB = (pll >> 16) & 0xFF;
+ NB = (pll >> 24) & 0xFF;
*MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
pll = NV_RD32(par->PMC, 0x4000);
case NV_ARCH_20:
case NV_ARCH_30:
default:
- if ((par->Chipset & 0xfff0) == 0x0240) {
- state->arbitration0 = 256;
- state->arbitration1 = 0x0480;
- } else if (((par->Chipset & 0xffff) == 0x01A0) ||
+ if (((par->Chipset & 0xffff) == 0x01A0) ||
((par->Chipset & 0xffff) == 0x01f0)) {
nForceUpdateArbitrationSettings(VClk,
pixelDepth * 8,
break;
case 0x0160:
case 0x01D0:
- case 0x0240:
NV_WR32(par->PMC, 0x1700,
NV_RD32(par->PFB, 0x020C));
NV_WR32(par->PMC, 0x1704, 0);
if(((par->Chipset & 0xfff0)
!= 0x0160) &&
((par->Chipset & 0xfff0)
- != 0x0220) &&
- ((par->Chipset & 0xfff0)
- != 0x240))
+ != 0x0220))
NV_WR32(par->PGRAPH,
0x6900 + i*4,
NV_RD32(par->PFB,