PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
- { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
{ 0, } /* terminate list */
};
MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
/* command line data, set in rivafb_setup() */
static int flatpanel __initdata = -1; /* Autodetect later */
static int forceCRTC __initdata = -1;
-static int noaccel __initdata = 0;
#ifdef CONFIG_MTRR
static int nomtrr __initdata = 0;
#endif
.activate = FB_ACTIVATE_NOW,
.height = -1,
.width = -1,
+ .accel_flags = FB_ACCELF_TEXT,
.pixclock = 39721,
.left_margin = 40,
.right_margin = 24,
bg = le16_to_cpu(bg);
fg = le16_to_cpu(fg);
- w = (w + 1) & ~1;
-
for (i = 0; i < h; i++) {
b = *data++;
reverse_order(&b);
newmode.ext.interlace = 0xff; /* interlace off */
if (par->riva.Architecture >= NV_ARCH_10)
- par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
+ par->riva.CURSOR = (U032 *)(info->screen_base + par->riva.CursorStart);
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
newmode.misc_output &= ~0x40;
par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
hDisplaySize, height, dotClock);
- newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
- 0xfff000ff;
+ newmode.ext.scale = par->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
if (par->FlatPanel == 1) {
newmode.ext.pixel |= (1 << 7);
newmode.ext.scale |= (1 << 8);
}
if (par->SecondCRTC) {
- newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
- ~0x00001000;
- newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
- 0x00001000;
+ newmode.ext.head = par->riva.PCRTC0[0x00000860/4] & ~0x00001000;
+ newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] | 0x00001000;
newmode.ext.crtcOwner = 3;
newmode.ext.pllsel |= 0x20000800;
newmode.ext.vpll2 = newmode.ext.vpll;
} else if (par->riva.twoHeads) {
- newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
- 0x00001000;
- newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
- ~0x00001000;
+ newmode.ext.head = par->riva.PCRTC0[0x00000860/4] | 0x00001000;
+ newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] & ~0x00001000;
newmode.ext.crtcOwner = 0;
- newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
+ newmode.ext.vpll2 = par->riva.PRAMDAC0[0x00000520/4];
}
if (par->FlatPanel == 1) {
newmode.ext.pixel |= (1 << 7);
riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
{
RIVA_FIFO_FREE(par->riva, Patt, 4);
- NV_WR32(&par->riva.Patt->Color0, 0, clr0);
- NV_WR32(&par->riva.Patt->Color1, 0, clr1);
- NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
- NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
+ par->riva.Patt->Color0 = clr0;
+ par->riva.Patt->Color1 = clr1;
+ par->riva.Patt->Monochrome[0] = pat0;
+ par->riva.Patt->Monochrome[1] = pat1;
}
/* acceleration routines */
{
riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
RIVA_FIFO_FREE(par->riva, Rop, 1);
- NV_WR32(&par->riva.Rop->Rop3, 0, rop);
+ par->riva.Rop->Rop3 = rop;
}
struct riva_par *par = (struct riva_par *) info->par;
RIVA_FIFO_FREE(par->riva, Clip, 2);
- NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
- NV_WR32(&par->riva.Clip->WidthHeight, 0,
- (info->var.xres_virtual & 0xffff) |
- (info->var.yres_virtual << 16));
+ par->riva.Clip->TopLeft = 0x0;
+ par->riva.Clip->WidthHeight = (info->var.xres_virtual & 0xffff) |
+ (info->var.yres_virtual << 16);
riva_set_rop_solid(par, 0xcc);
wait_for_idle(par);
}
par->state.flags |= VGA_SAVE_CMAP;
save_vga(&par->state);
#endif
+ riva_common_setup(par);
+ RivaGetConfig(&par->riva, par->Chipset);
/* vgaHWunlock() + riva unlock (0x7F) */
CRTCout(par, 0x11, 0xFF);
par->riva.LockUnlock(&par->riva, 0);
}
if (!strictmode) {
- if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
- !info->monspecs.dclkmax || !fb_validate_mode(var, info))
+ if (!fb_validate_mode(var, info))
mode_valid = 1;
}
}
}
- if (!mode_valid && info->monspecs.modedb_len)
+ if (!mode_valid && !list_empty(&info->modelist))
return -EINVAL;
if (var->xres_virtual < var->xres)
struct riva_par *par = (struct riva_par *) info->par;
NVTRACE_ENTER();
+ riva_common_setup(par);
+ RivaGetConfig(&par->riva, par->Chipset);
/* vgaHWunlock() + riva unlock (0x7F) */
CRTCout(par, 0x11, 0xFF);
par->riva.LockUnlock(&par->riva, 0);
+
riva_load_video_mode(info);
- if(!(info->flags & FBINFO_HWACCEL_DISABLED))
- riva_setup_accel(info);
+ riva_setup_accel(info);
- par->cursor_reset = 1;
+ memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
info->fix.visual = (info->var.bits_per_pixel == 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
- if (info->flags & FBINFO_HWACCEL_DISABLED)
- info->pixmap.scan_align = 1;
- else
- info->pixmap.scan_align = 4;
NVTRACE_LEAVE();
return 0;
}
vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
NVTRACE_ENTER();
-
- if (blank)
+ if (blank) {
tmp |= 0x20;
-
- switch (blank) {
- case FB_BLANK_UNBLANK:
- case FB_BLANK_NORMAL:
- break;
- case FB_BLANK_VSYNC_SUSPEND:
- vesa |= 0x80;
- break;
- case FB_BLANK_HSYNC_SUSPEND:
- vesa |= 0x40;
- break;
- case FB_BLANK_POWERDOWN:
- vesa |= 0xc0;
- break;
+ switch (blank - 1) {
+ case VESA_NO_BLANKING:
+ break;
+ case VESA_VSYNC_SUSPEND:
+ vesa |= 0x80;
+ break;
+ case VESA_HSYNC_SUSPEND:
+ vesa |= 0x40;
+ break;
+ case VESA_POWERDOWN:
+ vesa |= 0xc0;
+ break;
+ }
}
-
SEQout(par, 0x01, tmp);
CRTCout(par, 0x1a, vesa);
#endif
NVTRACE_LEAVE();
-
return 0;
}
struct riva_par *par = (struct riva_par *) info->par;
u_int color, rop = 0;
- if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
- cfb_fillrect(info, rect);
- return;
- }
-
if (info->var.bits_per_pixel == 8)
color = rect->color;
else {
riva_set_rop_solid(par, rop);
RIVA_FIFO_FREE(par->riva, Bitmap, 1);
- NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
+ par->riva.Bitmap->Color1A = color;
RIVA_FIFO_FREE(par->riva, Bitmap, 2);
- NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
- (rect->dx << 16) | rect->dy);
+ par->riva.Bitmap->UnclippedRectangle[0].TopLeft =
+ (rect->dx << 16) | rect->dy;
mb();
- NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
- (rect->width << 16) | rect->height);
+ par->riva.Bitmap->UnclippedRectangle[0].WidthHeight =
+ (rect->width << 16) | rect->height;
mb();
riva_set_rop_solid(par, 0xcc);
{
struct riva_par *par = (struct riva_par *) info->par;
- if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
- cfb_copyarea(info, region);
- return;
- }
-
RIVA_FIFO_FREE(par->riva, Blt, 3);
- NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
- (region->sy << 16) | region->sx);
- NV_WR32(&par->riva.Blt->TopLeftDst, 0,
- (region->dy << 16) | region->dx);
+ par->riva.Blt->TopLeftSrc = (region->sy << 16) | region->sx;
+ par->riva.Blt->TopLeftDst = (region->dy << 16) | region->dx;
mb();
- NV_WR32(&par->riva.Blt->WidthHeight, 0,
- (region->height << 16) | region->width);
+ par->riva.Blt->WidthHeight = (region->height << 16) | region->width;
mb();
}
struct riva_par *par = (struct riva_par *) info->par;
u32 fgx = 0, bgx = 0, width, tmp;
u8 *cdat = (u8 *) image->data;
- volatile u32 __iomem *d;
+ volatile u32 *d;
int i, size;
- if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
+ if (image->depth != 1) {
cfb_imageblit(info, image);
return;
}
}
RIVA_FIFO_FREE(par->riva, Bitmap, 7);
- NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
- (image->dy << 16) | (image->dx & 0xFFFF));
- NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
+ par->riva.Bitmap->ClipE.TopLeft =
+ (image->dy << 16) | (image->dx & 0xFFFF);
+ par->riva.Bitmap->ClipE.BottomRight =
(((image->dy + image->height) << 16) |
- ((image->dx + image->width) & 0xffff)));
- NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
- NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
- NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
- (image->height << 16) | ((image->width + 31) & ~31));
- NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
- (image->height << 16) | ((image->width + 31) & ~31));
- NV_WR32(&par->riva.Bitmap->PointE, 0,
- (image->dy << 16) | (image->dx & 0xFFFF));
+ ((image->dx + image->width) & 0xffff));
+ par->riva.Bitmap->Color0E = bgx;
+ par->riva.Bitmap->Color1E = fgx;
+ par->riva.Bitmap->WidthHeightInE =
+ (image->height << 16) | ((image->width + 31) & ~31);
+ par->riva.Bitmap->WidthHeightOutE =
+ (image->height << 16) | ((image->width + 31) & ~31);
+ par->riva.Bitmap->PointE =
+ (image->dy << 16) | (image->dx & 0xFFFF);
d = &par->riva.Bitmap->MonochromeData01E;
tmp = *((u32 *)cdat);
cdat = (u8 *)((u32 *)cdat + 1);
reverse_order(&tmp);
- NV_WR32(d, i*4, tmp);
+ d[i] = tmp;
}
size -= 16;
}
tmp = *((u32 *) cdat);
cdat = (u8 *)((u32 *)cdat + 1);
reverse_order(&tmp);
- NV_WR32(d, i*4, tmp);
+ d[i] = tmp;
}
}
}
struct riva_par *par = (struct riva_par *) info->par;
u8 data[MAX_CURS * MAX_CURS/8];
u16 fg, bg;
- int i, set = cursor->set;
-
- if (cursor->image.width > MAX_CURS ||
- cursor->image.height > MAX_CURS)
- return soft_cursor(info, cursor);
+ int i;
par->riva.ShowHideCursor(&par->riva, 0);
- if (par->cursor_reset) {
- set = FB_CUR_SETALL;
- par->cursor_reset = 0;
- }
-
- if (set & FB_CUR_SETSIZE)
- memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
-
- if (set & FB_CUR_SETPOS) {
+ if (cursor->set & FB_CUR_SETPOS) {
u32 xx, yy, temp;
+ info->cursor.image.dx = cursor->image.dx;
+ info->cursor.image.dy = cursor->image.dy;
yy = cursor->image.dy - info->var.yoffset;
xx = cursor->image.dx - info->var.xoffset;
temp = xx & 0xFFFF;
temp |= yy << 16;
- NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
+ par->riva.PRAMDAC[0x0000300/4] = temp;
+ }
+
+ if (cursor->set & FB_CUR_SETSIZE) {
+ info->cursor.image.height = cursor->image.height;
+ info->cursor.image.width = cursor->image.width;
+ memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
}
+ if (cursor->set & FB_CUR_SETCMAP) {
+ info->cursor.image.bg_color = cursor->image.bg_color;
+ info->cursor.image.fg_color = cursor->image.fg_color;
+ }
- if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
- u32 bg_idx = cursor->image.bg_color;
- u32 fg_idx = cursor->image.fg_color;
- u32 s_pitch = (cursor->image.width+7) >> 3;
+ if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETCUR)) {
+ u32 bg_idx = info->cursor.image.bg_color;
+ u32 fg_idx = info->cursor.image.fg_color;
+ u32 s_pitch = (info->cursor.image.width+7) >> 3;
u32 d_pitch = MAX_CURS/8;
u8 *dat = (u8 *) cursor->image.data;
- u8 *msk = (u8 *) cursor->mask;
- u8 *src;
+ u8 *msk = (u8 *) info->cursor.mask;
+ u8 src[64];
- src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
-
- if (src) {
- switch (cursor->rop) {
- case ROP_XOR:
- for (i = 0; i < s_pitch * cursor->image.height;
- i++)
- src[i] = dat[i] ^ msk[i];
- break;
- case ROP_COPY:
- default:
- for (i = 0; i < s_pitch * cursor->image.height;
- i++)
- src[i] = dat[i] & msk[i];
- break;
- }
-
- fb_sysmove_buf_aligned(info, &info->pixmap, data,
- d_pitch, src, s_pitch,
- cursor->image.height);
+ info->cursor.image.data = cursor->image.data;
+ switch (info->cursor.rop) {
+ case ROP_XOR:
+ for (i = 0; i < s_pitch * info->cursor.image.height;
+ i++)
+ src[i] = dat[i] ^ msk[i];
+ break;
+ case ROP_COPY:
+ default:
+ for (i = 0; i < s_pitch * info->cursor.image.height;
+ i++)
+ src[i] = dat[i] & msk[i];
+ break;
+ }
+
+ fb_sysmove_buf_aligned(info, &info->sprite, data, d_pitch, src,
+ s_pitch, info->cursor.image.height);
- bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
- ((info->cmap.green[bg_idx] & 0xf8) << 2) |
- ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
- 1 << 15;
+ bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
+ ((info->cmap.green[bg_idx] & 0xf8) << 2) |
+ ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
- fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
- ((info->cmap.green[fg_idx] & 0xf8) << 2) |
- ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
- 1 << 15;
+ fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
+ ((info->cmap.green[fg_idx] & 0xf8) << 2) |
+ ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
- par->riva.LockUnlock(&par->riva, 0);
+ par->riva.LockUnlock(&par->riva, 0);
- rivafb_load_cursor_image(par, data, bg, fg,
- cursor->image.width,
- cursor->image.height);
- kfree(src);
- }
+ rivafb_load_cursor_image(par, data, bg, fg,
+ info->cursor.image.width,
+ info->cursor.image.height);
}
-
- if (cursor->enable)
+ if (info->cursor.enable)
par->riva.ShowHideCursor(&par->riva, 1);
-
return 0;
}
| FBINFO_HWACCEL_FILLRECT
| FBINFO_HWACCEL_IMAGEBLIT
| FBINFO_MISC_MODESWITCHLATE;
-
- /* Accel seems to not work properly on NV30 yet...*/
- if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
- printk(KERN_DEBUG PFX "disabling acceleration\n");
- info->flags |= FBINFO_HWACCEL_DISABLED;
- }
-
info->var = rivafb_default_var;
info->fix.visual = (info->var.bits_per_pixel == 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
cmap_len = riva_get_cmap_len(&info->var);
fb_alloc_cmap(&info->cmap, cmap_len, 0);
- info->pixmap.size = 8 * 1024;
+ info->pixmap.size = 64 * 1024;
info->pixmap.buf_align = 4;
+ info->pixmap.scan_align = 4;
info->pixmap.flags = FB_PIXMAP_SYSTEM;
info->var.yres_virtual = -1;
NVTRACE_LEAVE();
pedid = (unsigned char *)
get_property(dp, propnames[i], NULL);
if (pedid != NULL) {
- par->EDID = pedid;
- NVTRACE("LCD found.\n");
- return 1;
+ par->EDID = pedid;
+ return 1;
}
}
}
NVTRACE_LEAVE();
- return 0;
+ return 0;
}
#endif /* CONFIG_PPC_OF */
for (i = par->bus; i >= 1; i--) {
riva_probe_i2c_connector(par, i, &par->EDID);
if (par->EDID) {
- printk(PFX "Found EDID Block from BUS %i\n", i);
+ printk("rivafb: Found EDID Block from BUS %i\n", i);
break;
}
}
var->bits_per_pixel = 8;
riva_update_var(var, &modedb);
}
+ var->accel_flags |= FB_ACCELF_TEXT;
NVTRACE_LEAVE();
}
NVTRACE_ENTER();
#ifdef CONFIG_PPC_OF
if (!riva_get_EDID_OF(info, pdev))
- printk(PFX "could not retrieve EDID from OF\n");
+ printk("rivafb: could not retrieve EDID from OF\n");
#elif CONFIG_FB_RIVA_I2C
if (!riva_get_EDID_i2c(info))
- printk(PFX "could not retrieve EDID from DDC/I2C\n");
+ printk("rivafb: could not retrieve EDID from DDC/I2C\n");
#endif
NVTRACE_LEAVE();
}
{
struct riva_par *default_par;
struct fb_info *info;
- int ret;
NVTRACE_ENTER();
assert(pd != NULL);
- info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
- if (!info) {
- printk (KERN_ERR PFX "could not allocate memory\n");
- ret = -ENOMEM;
- goto err_ret;
- }
- default_par = (struct riva_par *) info->par;
+ info = kmalloc(sizeof(struct fb_info), GFP_KERNEL);
+ if (!info)
+ goto err_out;
+
+ default_par = kmalloc(sizeof(struct riva_par), GFP_KERNEL);
+ if (!default_par)
+ goto err_out_kfree;
+
+ memset(info, 0, sizeof(struct fb_info));
+ memset(default_par, 0, sizeof(struct riva_par));
default_par->pdev = pd;
- info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
- if (info->pixmap.addr == NULL) {
- ret = -ENOMEM;
- goto err_framebuffer_release;
- }
- memset(info->pixmap.addr, 0, 8 * 1024);
+ info->pixmap.addr = kmalloc(64 * 1024, GFP_KERNEL);
+ if (info->pixmap.addr == NULL)
+ goto err_out_kfree1;
+ memset(info->pixmap.addr, 0, 64 * 1024);
- ret = pci_enable_device(pd);
- if (ret < 0) {
+ if (pci_enable_device(pd)) {
printk(KERN_ERR PFX "cannot enable PCI device\n");
- goto err_free_pixmap;
+ goto err_out_enable;
}
- ret = pci_request_regions(pd, "rivafb");
- if (ret < 0) {
+ if (pci_request_regions(pd, "rivafb")) {
printk(KERN_ERR PFX "cannot request PCI regions\n");
- goto err_disable_device;
+ goto err_out_request;
}
default_par->riva.Architecture = riva_get_arch(pd);
if(default_par->riva.Architecture == 0) {
printk(KERN_ERR PFX "unknown NV_ARCH\n");
- ret=-ENODEV;
- goto err_release_region;
+ goto err_out_kfree1;
}
if(default_par->riva.Architecture == NV_ARCH_10 ||
default_par->riva.Architecture == NV_ARCH_20 ||
rivafb_fix.mmio_len);
if (!default_par->ctrl_base) {
printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
- ret = -EIO;
- goto err_release_region;
+ goto err_out_free_base0;
}
+ info->par = default_par;
+
switch (default_par->riva.Architecture) {
case NV_ARCH_03:
/* Riva128's PRAMIN is in the "framebuffer" space
default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
if (!default_par->riva.PRAMIN) {
printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
- ret = -EIO;
- goto err_iounmap_ctrl_base;
+ goto err_out_free_nv3_pramin;
}
+ rivafb_fix.accel = FB_ACCEL_NV3;
break;
case NV_ARCH_04:
case NV_ARCH_10:
case NV_ARCH_20:
case NV_ARCH_30:
- default_par->riva.PCRTC0 =
- (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
- default_par->riva.PRAMIN =
- (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
+ default_par->riva.PCRTC0 = (unsigned *)(default_par->ctrl_base + 0x00600000);
+ default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000);
+ rivafb_fix.accel = FB_ACCEL_NV4;
break;
}
+
riva_common_setup(default_par);
if (default_par->riva.Architecture == NV_ARCH_03) {
- default_par->riva.PCRTC = default_par->riva.PCRTC0
- = default_par->riva.PGRAPH;
+ default_par->riva.PCRTC = default_par->riva.PCRTC0 = default_par->riva.PGRAPH;
}
rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
rivafb_fix.smem_len);
if (!info->screen_base) {
printk(KERN_ERR PFX "cannot ioremap FB base\n");
- ret = -EIO;
- goto err_iounmap_pramin;
+ goto err_out_free_base1;
}
#ifdef CONFIG_MTRR
riva_get_EDID(info, pd);
riva_get_edidinfo(info);
- ret=riva_set_fbinfo(info);
- if (ret < 0) {
+ if (riva_set_fbinfo(info) < 0) {
printk(KERN_ERR PFX "error setting initial video mode\n");
- goto err_iounmap_screen_base;
+ goto err_out_iounmap_fb;
}
fb_destroy_modedb(info->monspecs.modedb);
+ info->monspecs.modedb_len = 0;
info->monspecs.modedb = NULL;
- ret = register_framebuffer(info);
- if (ret < 0) {
+
+ if (register_framebuffer(info) < 0) {
printk(KERN_ERR PFX
"error registering riva framebuffer\n");
- goto err_iounmap_screen_base;
+ goto err_out_iounmap_fb;
}
pci_set_drvdata(pd, info);
NVTRACE_LEAVE();
return 0;
-err_iounmap_screen_base:
+err_out_iounmap_fb:
#ifdef CONFIG_FB_RIVA_I2C
riva_delete_i2c_busses((struct riva_par *) info->par);
#endif
iounmap(info->screen_base);
-err_iounmap_pramin:
+err_out_free_base1:
if (default_par->riva.Architecture == NV_ARCH_03)
- iounmap(default_par->riva.PRAMIN);
-err_iounmap_ctrl_base:
+ iounmap((caddr_t)default_par->riva.PRAMIN);
+err_out_free_nv3_pramin:
iounmap(default_par->ctrl_base);
-err_release_region:
+err_out_free_base0:
pci_release_regions(pd);
-err_disable_device:
+err_out_request:
pci_disable_device(pd);
-err_free_pixmap:
+err_out_enable:
kfree(info->pixmap.addr);
-err_framebuffer_release:
- framebuffer_release(info);
-err_ret:
- return ret;
+err_out_kfree1:
+ kfree(default_par);
+err_out_kfree:
+ kfree(info);
+err_out:
+ return -ENODEV;
}
static void __exit rivafb_remove(struct pci_dev *pd)
iounmap(par->ctrl_base);
iounmap(info->screen_base);
if (par->riva.Architecture == NV_ARCH_03)
- iounmap(par->riva.PRAMIN);
+ iounmap((caddr_t)par->riva.PRAMIN);
pci_release_regions(pd);
pci_disable_device(pd);
kfree(info->pixmap.addr);
- framebuffer_release(info);
+ kfree(par);
+ kfree(info);
pci_set_drvdata(pd, NULL);
NVTRACE_LEAVE();
}
#endif
} else if (!strncmp(this_opt, "strictmode", 10)) {
strictmode = 1;
- } else if (!strncmp(this_opt, "noaccel", 7)) {
- noaccel = 1;
} else
mode_option = this_opt;
}
return -ENODEV;
rivafb_setup(option);
#endif
- return pci_register_driver(&rivafb_driver);
+ if (pci_register_driver(&rivafb_driver) > 0)
+ return 0;
+ pci_unregister_driver(&rivafb_driver);
+ return -ENODEV;
}
}
module_exit(rivafb_exit);
-#endif /* MODULE */
-module_param(noaccel, bool, 0);
-MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
-module_param(flatpanel, int, 0);
+MODULE_PARM(flatpanel, "i");
MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
-module_param(forceCRTC, int, 0);
+MODULE_PARM(forceCRTC, "i");
MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
+
#ifdef CONFIG_MTRR
-module_param(nomtrr, bool, 0);
+MODULE_PARM(nomtrr, "i");
MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
#endif
-module_param(strictmode, bool, 0);
+MODULE_PARM(strictmode, "i");
MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
+#endif /* MODULE */
MODULE_AUTHOR("Ani Joshi, maintainer");
MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
git://git.onelab.eu / linux-2.6.git / blobdiff