#define PCICFG0_SIZE 0x01000000
#define PCICFG0_BASE 0xfa000000
+#define FLUSH_SIZE 0x00100000
+#define FLUSH_BASE 0xf9000000
+
#define PCIMEM_SIZE 0x01000000
#define PCIMEM_BASE 0xf0000000
#define PCIMEM_SIZE 0x80000000
#define PCIMEM_BASE 0x80000000
+#define FLUSH_SIZE 0x00100000
+#define FLUSH_BASE 0x7e000000
+
#define WFLUSH_SIZE 0x01000000
#define WFLUSH_BASE 0x7d000000
#define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5))
#define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6))
+#define FLUSH_BASE_PHYS 0x50000000
#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108)