fedora core 6 1.2949 + vserver 2.2.0

[linux-2.6.git] / include / asm-arm / arch-s3c2410 / regs-dsc.h

diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index 0da1ec7..c074851 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -1,4 +1,4 @@
-/* linux/include/asm/hardware/s3c2410/regs-dsc.h
+/* linux/include/asm-arm/arch-s3c2410/regs-dsc.h
  *
  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
  *                   http://www.simtec.co.uk/products/SWLINUX/
@@ -7,28 +7,29 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- * S3C2440 Signal Drive Strength Control
- *
- *  Changelog:
- *    11-Aug-2004     BJD     Created file
- *    25-Aug-2004     BJD     Added the _SELECT_* defs for using with functions
+ * S3C2440/S3C2412 Signal Drive Strength Control
 */
 
 
 #ifndef __ASM_ARCH_REGS_DSC_H
 #define __ASM_ARCH_REGS_DSC_H "2440-dsc"
 
-#ifdef CONFIG_CPU_S3C2440
+#if defined(CONFIG_CPU_S3C2412)
+#define S3C2412_DSC0      S3C2410_GPIOREG(0xdc)
+#define S3C2412_DSC1      S3C2410_GPIOREG(0xe0)
+#endif
+
+#if defined(CONFIG_CPU_S3C2440)
 
-#define S3C2440_DSC0      S3C2410_GPIOREG(0xc0)
-#define S3C2440_DSC1      S3C2410_GPIOREG(0xc4)
+#define S3C2440_DSC0      S3C2410_GPIOREG(0xc4)
+#define S3C2440_DSC1      S3C2410_GPIOREG(0xc8)
 
 #define S3C2440_SELECT_DSC0 (0)
 #define S3C2440_SELECT_DSC1 (1<<31)
 
 #define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
 
-#define S3C2440_DSC0_ENABLE     (1<<31)
+#define S3C2440_DSC0_DISABLE   (1<<31)
 
 #define S3C2440_DSC0_ADDR       (S3C2440_SELECT_DSC0 | 8)
 #define S3C2440_DSC0_ADDR_12mA  (0<<8)
@@ -69,19 +70,19 @@
 #define S3C2440_DSC0_DATA0_6mA  (3<<0)
 #define S3C2440_DSC0_DATA0_MASK (3<<0)
 
-#define S3C2440_DSC1_SCK0       (S3C2440_SELECT_DSC1 | 28)
-#define S3C2440_DSC1_SCK0_12mA  (0<<28)
-#define S3C2440_DSC1_SCK0_10mA  (1<<28)
-#define S3C2440_DSC1_SCK0_8mA   (2<<28)
-#define S3C2440_DSC1_SCK0_6mA   (3<<28)
-#define S3C2440_DSC1_SCK0_MASK  (3<<28)
+#define S3C2440_DSC1_SCK1       (S3C2440_SELECT_DSC1 | 28)
+#define S3C2440_DSC1_SCK1_12mA  (0<<28)
+#define S3C2440_DSC1_SCK1_10mA  (1<<28)
+#define S3C2440_DSC1_SCK1_8mA   (2<<28)
+#define S3C2440_DSC1_SCK1_6mA   (3<<28)
+#define S3C2440_DSC1_SCK1_MASK  (3<<28)
 
-#define S3C2440_DSC1_SCK1       (S3C2440_SELECT_DSC1 | 26)
-#define S3C2440_DSC1_SCK1_12mA  (0<<26)
-#define S3C2440_DSC1_SCK1_10mA  (1<<26)
-#define S3C2440_DSC1_SCK1_8mA   (2<<26)
-#define S3C2440_DSC1_SCK1_6mA   (3<<26)
-#define S3C2440_DSC1_SCK1_MASK  (3<<26)
+#define S3C2440_DSC1_SCK0       (S3C2440_SELECT_DSC1 | 26)
+#define S3C2440_DSC1_SCK0_12mA  (0<<26)
+#define S3C2440_DSC1_SCK0_10mA  (1<<26)
+#define S3C2440_DSC1_SCK0_8mA   (2<<26)
+#define S3C2440_DSC1_SCK0_6mA   (3<<26)
+#define S3C2440_DSC1_SCK0_MASK  (3<<26)
 
 #define S3C2440_DSC1_SCKE       (S3C2440_SELECT_DSC1 | 24)
 #define S3C2440_DSC1_SCKE_10mA  (0<<24)
@@ -170,7 +171,7 @@
 #define S3C2440_DSC1_CS1_4mA    (3<<2)
 #define S3C2440_DSC1_CS1_MASK   (3<<2)
 
-#define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0
+#define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0)
 #define S3C2440_DSC1_CS0_10mA   (0<<0)
 #define S3C2440_DSC1_CS0_8mA    (1<<0)
 #define S3C2440_DSC1_CS0_6mA    (2<<0)