vserver 1.9.5.x5

[linux-2.6.git] / include / asm-arm / arch-s3c2410 / regs-gpio.h

diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 05eb116..07c17f9 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -1,4 +1,4 @@
-/* linux/include/asm/hardware/s3c2410/
+/* linux/include/asm/hardware/s3c2410/regs-gpio.h
  *
  * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
  *                        http://www.simtec.co.uk/products/SWLINUX/
@@ -15,6 +15,9 @@
  *    12-03-2004     BJD     Updated include protection
  *    20-07-2004     BJD     Added GPIO pin numbers, added Port A definitions
  *    04-10-2004     BJD     Fixed number of bugs, added EXT IRQ filter defs
+ *    17-10-2004     BJD     Added GSTATUS1 register definitions
+ *    18-11-2004     BJD     Fixed definitions of GPE3, GPE4, GPE5 and GPE6
+ *    18-11-2004     BJD     Added S3C2440 AC97 controls
 */
 
 
@@ -423,12 +426,14 @@
 #define S3C2410_GPE3_INP       (0x00 << 6)
 #define S3C2410_GPE3_OUTP      (0x01 << 6)
 #define S3C2410_GPE3_I2SSDI    (0x02 << 6)
+#define S3C2410_GPE3_nSS0      (0x03 << 6)
 #define S3C2410_GPE3_MASK      (0x03 << 6)
 
 #define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
 #define S3C2410_GPE4_INP       (0x00 << 8)
 #define S3C2410_GPE4_OUTP      (0x01 << 8)
 #define S3C2410_GPE4_I2SSDO    (0x02 << 8)
+#define S3C2410_GPE4_I2SSDI    (0x03 << 8)
 #define S3C2410_GPE4_MASK      (0x03 << 8)
 
 #define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
@@ -439,12 +444,12 @@
 #define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
 #define S3C2410_GPE6_INP       (0x00 << 12)
 #define S3C2410_GPE6_OUTP      (0x01 << 12)
-#define S3C2410_GPE6_SDCLK     (0x02 << 12)
+#define S3C2410_GPE6_SDCMD     (0x02 << 12)
 
 #define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
 #define S3C2410_GPE7_INP       (0x00 << 14)
 #define S3C2410_GPE7_OUTP      (0x01 << 14)
-#define S3C2410_GPE7_SDCMD     (0x02 << 14)
+#define S3C2410_GPE7_SDDAT0    (0x02 << 14)
 
 #define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
 #define S3C2410_GPE8_INP       (0x00 << 16)
@@ -488,6 +493,12 @@
 #define S3C2410_GPE15_IICSDA   (0x02 << 30)
 #define S3C2410_GPE15_MASK     (0x03 << 30)
 
+#define S3C2440_GPE0_ACSYNC    (0x03 << 0)
+#define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
+#define S3C2440_GPE2_ACRESET   (0x03 << 4)
+#define S3C2440_GPE3_ACIN      (0x03 << 6)
+#define S3C2440_GPE4_ACOUT     (0x03 << 8)
+
 #define S3C2410_GPE_PUPDIS(x)  (1<<(x))
 
 /* Port F consists of 8 GPIO/Special function
@@ -806,8 +817,12 @@
 #define S3C2410_GSTATUS0_RnB      (1<<1)
 #define S3C2410_GSTATUS0_nBATTFLT  (1<<0)
 
+#define S3C2410_GSTATUS1_IDMASK           (0xffff0000)
+#define S3C2410_GSTATUS1_2410     (0x32410000)
+#define S3C2410_GSTATUS1_2440     (0x32440000)
+
 #define S3C2410_GSTATUS2_WTRESET   (1<<2)
-#define S3C2410_GSTATUs2_OFFRESET  (1<<1)
+#define S3C2410_GSTATUS2_OFFRESET  (1<<1)
 #define S3C2410_GSTATUS2_PONRESET  (1<<0)
 
 #endif /* __ASM_ARCH_REGS_GPIO_H */