#define PLD(code...)
#endif
-#define MODE_USR USR_MODE
-#define MODE_FIQ FIQ_MODE
-#define MODE_IRQ IRQ_MODE
-#define MODE_SVC SVC_MODE
-
-#define DEFAULT_FIQ MODE_FIQ
-
/*
- * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
+ * Enable and disable interrupts
*/
-#ifdef __STDC__
-#define LOADREGS(cond, base, reglist...)\
- ldm##cond base,reglist
+#if __LINUX_ARM_ARCH__ >= 6
+ .macro disable_irq
+ cpsid i
+ .endm
+
+ .macro enable_irq
+ cpsie i
+ .endm
#else
-#define LOADREGS(cond, base, reglist...)\
- ldm/**/cond base,reglist
-#endif
+ .macro disable_irq
+ msr cpsr_c, #PSR_I_BIT | SVC_MODE
+ .endm
-/*
- * Build a return instruction for this processor type.
- */
-#define RETINSTR(instr, regs...)\
- instr regs
+ .macro enable_irq
+ msr cpsr_c, #SVC_MODE
+ .endm
+#endif
/*
* Save the current IRQ state and disable IRQs. Note that this macro
* assumes FIQs are enabled, and that the processor is in SVC mode.
*/
- .macro save_and_disable_irqs, oldcpsr, temp
+ .macro save_and_disable_irqs, oldcpsr
mrs \oldcpsr, cpsr
- mov \temp, #PSR_I_BIT | MODE_SVC
- msr cpsr_c, \temp
+ disable_irq
.endm
/*
msr cpsr_c, \oldcpsr
.endm
-/*
- * These two are used to save LR/restore PC over a user-based access.
- * The old 26-bit architecture requires that we do. On 32-bit
- * architecture, we can safely ignore this requirement.
- */
- .macro save_lr
- .endm
-
- .macro restore_pc
- mov pc, lr
- .endm
-
#define USER(x...) \
9999: x; \
.section __ex_table,"a"; \