char x86_model_id[64];
int x86_cache_size; /* in KB - valid for CPUS which support this
call */
+ int x86_cache_alignment; /* In bytes */
int fdiv_bug;
int f00f_bug;
int coma_bug;
/*
* Bus types (default is ISA, but people can check others with these..)
- * pc98 indicates PC98 systems (CBUS)
*/
extern int MCA_bus;
-#ifdef CONFIG_X86_PC9800
-#define pc98 1
-#else
-#define pc98 0
-#endif
static inline void __monitor(const void *eax, unsigned long ecx,
unsigned long edx)
#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
/*
- * Size of io_bitmap, covering ports 0 to 0x3ff.
+ * Size of io_bitmap.
*/
-#define IO_BITMAP_BITS 1024
+#define IO_BITMAP_BITS 65536
#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
/*
* pads the TSS to be cacheline-aligned (size is 0x100)
*/
- unsigned long __cacheline_filler[5];
+ unsigned long __cacheline_filler[37];
/*
* .. and then another 0x100 bytes for emergency kernel stack
*/
extern void select_idle_routine(const struct cpuinfo_x86 *c);
+#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
+
+#ifdef CONFIG_SCHED_SMT
+#define ARCH_HAS_SCHED_DOMAIN
+#define ARCH_HAS_SCHED_WAKE_IDLE
+#endif
+
#endif /* __ASM_I386_PROCESSOR_H */