#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
-#define PAL_PREFETCH_VISIBILITY 41
+#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
+#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
+#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
#define PAL_VM_TR_READ 261 /* read contents of translation register */
+#define PAL_GET_PSTATE 262 /* get the current P-state */
+#define PAL_SET_PSTATE 263 /* set the P-state */
#ifndef __ASSEMBLY__
#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
typedef struct pal_freq_ratio {
- u64 den : 32, num : 32; /* numerator & denominator */
+ u32 den, num; /* numerator & denominator */
} itc_ratio, proc_ratio;
typedef union pal_cache_config_info_1_s {
typedef union pal_cache_config_info_2_s {
struct {
- u64 cache_size : 32, /*cache size in bytes*/
+ u32 cache_size; /*cache size in bytes*/
- alias_boundary : 8, /* 39-32 aliased addr
+ u32 alias_boundary : 8, /* 39-32 aliased addr
* separation for max
* performance.
*/
ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
{
struct ia64_pal_retval iprv;
- PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
+ PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
if (vector)
*vector = iprv.v0;
*progress = iprv.v1;
return iprv.status;
}
+/* Get the current P-state information */
+static inline s64
+ia64_pal_get_pstate (u64 *pstate_index)
+{
+ struct ia64_pal_retval iprv;
+ PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
+ *pstate_index = iprv.v0;
+ return iprv.status;
+}
+
+/* Set the P-state */
+static inline s64
+ia64_pal_set_pstate (u64 pstate_index)
+{
+ struct ia64_pal_retval iprv;
+ PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
+ return iprv.status;
+}
+
/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
* suspended, but cache and TLB coherency is maintained.
*/
ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
{
struct ia64_pal_retval iprv;
- PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)__pa(tr_buffer));
+ PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
if (tr_valid)
tr_valid->piv_val = iprv.v0;
return iprv.status;
}
+/*
+ * PAL_PREFETCH_VISIBILITY transaction types
+ */
+#define PAL_VISIBILITY_VIRTUAL 0
+#define PAL_VISIBILITY_PHYSICAL 1
+
+/*
+ * PAL_PREFETCH_VISIBILITY return codes
+ */
+#define PAL_VISIBILITY_OK 1
+#define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
+#define PAL_VISIBILITY_INVAL_ARG -2
+#define PAL_VISIBILITY_ERROR -3
+
static inline s64
-ia64_pal_prefetch_visibility (void)
+ia64_pal_prefetch_visibility (s64 trans_type)
{
struct ia64_pal_retval iprv;
- PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, 0, 0, 0);
+ PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
return iprv.status;
}
+/* data structure for getting information on logical to physical mappings */
+typedef union pal_log_overview_u {
+ struct {
+ u64 num_log :16, /* Total number of logical
+ * processors on this die
+ */
+ tpc :8, /* Threads per core */
+ reserved3 :8, /* Reserved */
+ cpp :8, /* Cores per processor */
+ reserved2 :8, /* Reserved */
+ ppid :8, /* Physical processor ID */
+ reserved1 :8; /* Reserved */
+ } overview_bits;
+ u64 overview_data;
+} pal_log_overview_t;
+
+typedef union pal_proc_n_log_info1_u{
+ struct {
+ u64 tid :16, /* Thread id */
+ reserved2 :16, /* Reserved */
+ cid :16, /* Core id */
+ reserved1 :16; /* Reserved */
+ } ppli1_bits;
+ u64 ppli1_data;
+} pal_proc_n_log_info1_t;
+
+typedef union pal_proc_n_log_info2_u {
+ struct {
+ u64 la :16, /* Logical address */
+ reserved :48; /* Reserved */
+ } ppli2_bits;
+ u64 ppli2_data;
+} pal_proc_n_log_info2_t;
+
+typedef struct pal_logical_to_physical_s
+{
+ pal_log_overview_t overview;
+ pal_proc_n_log_info1_t ppli1;
+ pal_proc_n_log_info2_t ppli2;
+} pal_logical_to_physical_t;
+
+#define overview_num_log overview.overview_bits.num_log
+#define overview_tpc overview.overview_bits.tpc
+#define overview_cpp overview.overview_bits.cpp
+#define overview_ppid overview.overview_bits.ppid
+#define log1_tid ppli1.ppli1_bits.tid
+#define log1_cid ppli1.ppli1_bits.cid
+#define log2_la ppli2.ppli2_bits.la
+
+/* Get information on logical to physical processor mappings. */
+static inline s64
+ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
+{
+ struct ia64_pal_retval iprv;
+
+ PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
+
+ if (iprv.status == PAL_STATUS_SUCCESS)
+ {
+ mapping->overview.overview_data = iprv.v0;
+ mapping->ppli1.ppli1_data = iprv.v1;
+ mapping->ppli2.ppli2_data = iprv.v2;
+ }
+
+ return iprv.status;
+}
+
+typedef struct pal_cache_shared_info_s
+{
+ u64 num_shared;
+ pal_proc_n_log_info1_t ppli1;
+ pal_proc_n_log_info2_t ppli2;
+} pal_cache_shared_info_t;
+
+/* Get information on logical to physical processor mappings. */
+static inline s64
+ia64_pal_cache_shared_info(u64 level,
+ u64 type,
+ u64 proc_number,
+ pal_cache_shared_info_t *info)
+{
+ struct ia64_pal_retval iprv;
+
+ PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
+
+ if (iprv.status == PAL_STATUS_SUCCESS) {
+ info->num_shared = iprv.v0;
+ info->ppli1.ppli1_data = iprv.v1;
+ info->ppli2.ppli2_data = iprv.v2;
+ }
+
+ return iprv.status;
+}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_IA64_PAL_H */
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