* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) MIPS Technologies, Inc.
+ * written by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef _ASM_HAZARDS_H
#define _ASM_HAZARDS_H
-#include <linux/config.h>
#ifdef __ASSEMBLY__
+#define ASMMACRO(name, code...) .macro name; code; .endm
+#else
- .macro _ssnop
- sll $0, $2, 1
- .endm
+#define ASMMACRO(name, code...) \
+__asm__(".macro " #name "; " #code "; .endm"); \
+ \
+static inline void name(void) \
+{ \
+ __asm__ __volatile__ (#name); \
+}
-/*
- * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
- * use of the JTLB for instructions should not occur for 4 cpu cycles and use
- * for data translations should not occur for 3 cpu cycles.
- */
-#ifdef CONFIG_CPU_RM9000
+#endif
-#define mtc0_tlbw_hazard \
- .set push; \
- .set mips32; \
- _ssnop; _ssnop; _ssnop; _ssnop; \
- .set pop
+ASMMACRO(_ssnop,
+ sll $0, $0, 1
+ )
-#define tlbw_eret_hazard \
- .set push; \
- .set mips32; \
- _ssnop; _ssnop; _ssnop; _ssnop; \
- .set pop
-
-#else
+ASMMACRO(_ehb,
+ sll $0, $0, 3
+ )
/*
- * The taken branch will result in a two cycle penalty for the two killed
- * instructions on R4000 / R4400. Other processors only have a single cycle
- * hazard so this is nice trick to have an optimal code for a range of
- * processors.
+ * TLB hazards
*/
-#define mtc0_tlbw_hazard \
- b . + 8
-#define tlbw_eret_hazard
-#endif
+#if defined(CONFIG_CPU_MIPSR2)
/*
- * mtc0->mfc0 hazard
- * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
- * It is a MIPS32R2 processor so ehb will clear the hazard.
+ * MIPSR2 defines ehb for hazard avoidance
*/
-#ifdef CONFIG_CPU_MIPSR2
+ASMMACRO(mtc0_tlbw_hazard,
+ _ehb
+ )
+ASMMACRO(tlbw_use_hazard,
+ _ehb
+ )
+ASMMACRO(tlb_probe_hazard,
+ _ehb
+ )
+ASMMACRO(irq_enable_hazard,
+ )
+ASMMACRO(irq_disable_hazard,
+ _ehb
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ _ehb
+ )
/*
- * Use a macro for ehb unless explicit support for MIPSR2 is enabled
+ * gcc has a tradition of misscompiling the previous construct using the
+ * address of a label as argument to inline assembler. Gas otoh has the
+ * annoying difference between la and dla which are only usable for 32-bit
+ * rsp. 64-bit code, so can't be used without conditional compilation.
+ * The alterantive is switching the assembler to 64-bit code which happens
+ * to work right even for 32-bit code ...
*/
- .macro ehb
- sll $0, $0, 3
- .endm
-
-#define irq_enable_hazard \
- ehb # irq_enable_hazard
-
-#define irq_disable_hazard \
- ehb # irq_disable_hazard
-
-#else
-
-#define irq_enable_hazard
-#define irq_disable_hazard
-
-#endif
-
-#else /* __ASSEMBLY__ */
-
-/*
- * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
- * use of the JTLB for instructions should not occur for 4 cpu cycles and use
- * for data translations should not occur for 3 cpu cycles.
- */
-#ifdef CONFIG_CPU_RM9000
-
-#define mtc0_tlbw_hazard() \
+#define instruction_hazard() \
+do { \
+ unsigned long tmp; \
+ \
__asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
- ".set\tmips0")
+ " .set mips64r2 \n" \
+ " dla %0, 1f \n" \
+ " jr.hb %0 \n" \
+ " .set mips0 \n" \
+ "1: \n" \
+ : "=r" (tmp)); \
+} while (0)
-#define tlbw_use_hazard() \
- __asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
- ".set\tmips0")
-#else
+#elif defined(CONFIG_CPU_R10000)
/*
- * Overkill warning ...
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
*/
-#define mtc0_tlbw_hazard() \
- __asm__ __volatile__( \
- ".set noreorder\n\t" \
- "nop; nop; nop; nop; nop; nop;\n\t" \
- ".set reorder\n\t")
-
-#define tlbw_use_hazard() \
- __asm__ __volatile__( \
- ".set noreorder\n\t" \
- "nop; nop; nop; nop; nop; nop;\n\t" \
- ".set reorder\n\t")
-#endif
+ASMMACRO(mtc0_tlbw_hazard,
+ )
+ASMMACRO(tlbw_use_hazard,
+ )
+ASMMACRO(tlb_probe_hazard,
+ )
+ASMMACRO(irq_enable_hazard,
+ )
+ASMMACRO(irq_disable_hazard,
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ )
+#define instruction_hazard() do { } while (0)
+
+#elif defined(CONFIG_CPU_RM9000)
/*
- * mtc0->mfc0 hazard
- * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
- * It is a MIPS32R2 processor so ehb will clear the hazard.
+ * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
+ * use of the JTLB for instructions should not occur for 4 cpu cycles and use
+ * for data translations should not occur for 3 cpu cycles.
*/
-#ifdef CONFIG_CPU_MIPSR2
-/*
- * Use a macro for ehb unless explicit support for MIPSR2 is enabled
- */
-__asm__(
- " .macro ehb \n\t"
- " sll $0, $0, 3 \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_enable_hazard \n\t"
- " ehb \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_disable_hazard \n\t"
- " ehb \n\t"
- " .endm");
-
-#define irq_enable_hazard() \
- __asm__ __volatile__( \
- "ehb\t\t\t\t# irq_enable_hazard")
-
-#define irq_disable_hazard() \
- __asm__ __volatile__( \
- "ehb\t\t\t\t# irq_disable_hazard")
-
-#elif defined(CONFIG_CPU_R10000)
+ASMMACRO(mtc0_tlbw_hazard,
+ _ssnop; _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(tlbw_use_hazard,
+ _ssnop; _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(tlb_probe_hazard,
+ _ssnop; _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(irq_enable_hazard,
+ )
+ASMMACRO(irq_disable_hazard,
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ )
+#define instruction_hazard() do { } while (0)
+
+#elif defined(CONFIG_CPU_SB1)
/*
- * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ * Mostly like R4000 for historic reasons
*/
-
-__asm__(
- " .macro\tirq_enable_hazard \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_disable_hazard \n\t"
- " .endm");
-
-#define irq_enable_hazard() do { } while (0)
-#define irq_disable_hazard() do { } while (0)
+ASMMACRO(mtc0_tlbw_hazard,
+ )
+ASMMACRO(tlbw_use_hazard,
+ )
+ASMMACRO(tlb_probe_hazard,
+ )
+ASMMACRO(irq_enable_hazard,
+ )
+ASMMACRO(irq_disable_hazard,
+ _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ )
+#define instruction_hazard() do { } while (0)
#else
/*
- * Default for classic MIPS processors. Assume worst case hazards but don't
- * care about the irq_enable_hazard - sooner or later the hardware will
- * enable it and we don't care when exactly.
+ * Finally the catchall case for all other processors including R4000, R4400,
+ * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
+ *
+ * The taken branch will result in a two cycle penalty for the two killed
+ * instructions on R4000 / R4400. Other processors only have a single cycle
+ * hazard so this is nice trick to have an optimal code for a range of
+ * processors.
*/
-
-__asm__(
- " .macro _ssnop \n\t"
- " sll $0, $2, 1 \n\t"
- " .endm \n\t"
- " \n\t"
- " # \n\t"
- " # There is a hazard but we do not care \n\t"
- " # \n\t"
- " .macro\tirq_enable_hazard \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_disable_hazard \n\t"
- " _ssnop; _ssnop; _ssnop \n\t"
- " .endm");
-
-#define irq_enable_hazard() do { } while (0)
-#define irq_disable_hazard() \
- __asm__ __volatile__( \
- "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
+ASMMACRO(mtc0_tlbw_hazard,
+ nop; nop
+ )
+ASMMACRO(tlbw_use_hazard,
+ nop; nop; nop
+ )
+ASMMACRO(tlb_probe_hazard,
+ nop; nop; nop
+ )
+ASMMACRO(irq_enable_hazard,
+ )
+ASMMACRO(irq_disable_hazard,
+ nop; nop; nop
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ _ssnop; _ssnop; _ssnop;
+ )
+#define instruction_hazard() do { } while (0)
#endif
-#endif /* __ASSEMBLY__ */
-
#endif /* _ASM_HAZARDS_H */
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