Merge to Fedora kernel-2.6.18-1.2224_FC5 patched with stable patch-2.6.18.1-vs2.0...

[linux-2.6.git] / include / asm-mips / pgtable-bits.h

diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 22d1983..7494ba9 100644 (file)
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -10,7 +10,6 @@
 #ifndef _ASM_PGTABLE_BITS_H
 #define _ASM_PGTABLE_BITS_H
 
-#include <linux/config.h>
 
 /*
  * Note that we shift the lower 32bits of each EntryLo[01] entry
@@ -33,6 +32,32 @@
  * unpredictable things.  The code (when it is written) to deal with
  * this problem will be in the update_mmu_cache() code for the r4k.
  */
+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
+
+#define _PAGE_PRESENT               (1<<6)  /* implemented in software */
+#define _PAGE_READ                  (1<<7)  /* implemented in software */
+#define _PAGE_WRITE                 (1<<8)  /* implemented in software */
+#define _PAGE_ACCESSED              (1<<9)  /* implemented in software */
+#define _PAGE_MODIFIED              (1<<10) /* implemented in software */
+#define _PAGE_FILE                  (1<<10)  /* set:pagecache unset:swap */
+
+#define _PAGE_R4KBUG                (1<<0)  /* workaround for r4k bug  */
+#define _PAGE_GLOBAL                (1<<0)
+#define _PAGE_VALID                 (1<<1)
+#define _PAGE_SILENT_READ           (1<<1)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<2)  /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<2)
+#define _CACHE_MASK                 (7<<3)
+
+/* MIPS32 defines only values 2 and 3. The rest are implementation
+ * dependent.
+ */
+#define _CACHE_UNCACHED             (2<<3)
+#define _CACHE_CACHABLE_NONCOHERENT (3<<3)
+#define _CACHE_CACHABLE_COW         (3<<3)  /* Au1x                    */
+
+#else
+
 #define _PAGE_PRESENT               (1<<0)  /* implemented in software */
 #define _PAGE_READ                  (1<<1)  /* implemented in software */
 #define _PAGE_WRITE                 (1<<2)  /* implemented in software */
@@ -60,7 +85,7 @@
 #define _PAGE_SILENT_WRITE          (1<<8)
 #define _CACHE_MASK                 (7<<9)
 
-#if defined(CONFIG_CPU_SB1)
+#ifdef CONFIG_CPU_SB1
 
 /* No penalty for being coherent on the SB1, so just
    use it for "noncoherent" spaces, too.  Shouldn't hurt. */
@@ -70,6 +95,20 @@
 #define _CACHE_CACHABLE_NONCOHERENT (5<<9)
 #define _CACHE_UNCACHED_ACCELERATED (7<<9)
 
+#elif defined(CONFIG_CPU_RM9000)
+
+#define _CACHE_WT                      (0 << 9)
+#define _CACHE_WTWA                    (1 << 9)
+#define _CACHE_UC_B                    (2 << 9)
+#define _CACHE_WB                      (3 << 9)
+#define _CACHE_CWBEA                   (4 << 9)
+#define _CACHE_CWB                     (5 << 9)
+#define _CACHE_UCNB                    (6 << 9)
+#define _CACHE_FPC                     (7 << 9)
+
+#define _CACHE_UNCACHED                        _CACHE_UC_B
+#define _CACHE_CACHABLE_NONCOHERENT    _CACHE_WB
+
 #else
 
 #define _CACHE_CACHABLE_NO_WA       (0<<9)  /* R4600 only              */
@@ -83,6 +122,7 @@
 
 #endif
 #endif
+#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */
 
 #define __READABLE     (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
 #define __WRITEABLE    (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -93,10 +133,16 @@
 #define PAGE_CACHABLE_DEFAULT  _CACHE_UNCACHED
 #elif defined(CONFIG_DMA_NONCOHERENT)
 #define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_NONCOHERENT
+#elif defined(CONFIG_CPU_RM9000)
+#define PAGE_CACHABLE_DEFAULT  _CACHE_CWB
 #else
 #define PAGE_CACHABLE_DEFAULT  _CACHE_CACHABLE_COW
 #endif
 
+#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR)
+#define CONF_CM_DEFAULT                (PAGE_CACHABLE_DEFAULT >> 3)
+#else
 #define CONF_CM_DEFAULT                (PAGE_CACHABLE_DEFAULT >> 9)
+#endif
 
 #endif /* _ASM_PGTABLE_BITS_H */