#ifndef _ASM_WAR_H
#define _ASM_WAR_H
-#include <linux/config.h>
/*
* Another R4600 erratum. Due to the lack of errata information the exact
/*
* But the RM200C seems to have been shipped only with V2.0 R4600s
*/
-#ifdef CONFIG_SNI_RM200_PCI
+#ifdef CONFIG_SNI_RM
#define R4600_V2_HIT_CACHEOP_WAR 1
*/
#define BCM1250_M3_WAR 1
-/*
+/*
* This is a DUART workaround related to glitches around register accesses
*/
#define SIBYTE_1956_WAR 1
/*
* Fill buffers not flushed on CACHE instructions
- *
+ *
* Hit_Invalidate_I cacheops invalidate an icache line but the refill
* for that line can get stale data from the fill buffer instead of
* accessing memory if the previous icache miss was also to that line.
* On the RM9000 there is a problem which makes the CreateDirtyExclusive
* cache operation unusable on SMP systems.
*/
-#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE)
+#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
+ defined(CONFIG_BASLER_EXCITE)
#define RM9000_CDEX_SMP_WAR 1
#endif
+/*
+ * The RM9000 has a bug (though PMC-Sierra opposes it being called that)
+ * where invalid instructions in the same I-cache line worth of instructions
+ * being fetched may case spurious exceptions.
+ */
+#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
+ defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
+#define ICACHE_REFILLS_WORKAROUND_WAR 1
+#endif
+
+
+/*
+ * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
+ * may cause ll / sc and lld / scd sequences to execute non-atomically.
+ */
+#ifdef CONFIG_SGI_IP27
+#define R10000_LLSC_WAR 1
+#endif
+
/*
* Workarounds default to off
*/
+#ifndef ICACHE_REFILLS_WORKAROUND_WAR
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#endif
#ifndef R4600_V1_INDEX_ICACHEOP_WAR
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#endif
#ifndef RM9000_CDEX_SMP_WAR
#define RM9000_CDEX_SMP_WAR 0
#endif
+#ifndef R10000_LLSC_WAR
+#define R10000_LLSC_WAR 0
+#endif
#endif /* _ASM_WAR_H */