*
* PPC44x definitions
*
- * Matt Porter <mporter@mvista.com>
+ * Matt Porter <mporter@kernel.crashing.org>
*
- * Copyright 2002-2003 MontaVista Software Inc.
+ * Copyright 2002-2005 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
#ifndef __ASM_IBM44x_H__
#define __ASM_IBM44x_H__
-#include <linux/config.h>
-
-#ifndef __ASSEMBLY__
-/*
- * Data structure defining board information maintained by the boot
- * ROM on IBM's "Ebony" evaluation board. An effort has been made to
- * keep the field names consistent with the 8xx 'bd_t' board info
- * structures.
- *
- * Ebony firmware stores MAC addresses in the F/W VPD area. The
- * firmware must store the other dynamic values in NVRAM like on
- * the previous 40x systems so they should be accessible if we
- * really want them.
- */
-typedef struct board_info {
- unsigned char bi_enetaddr[2][6]; /* EMAC addresses */
- unsigned int bi_opb_busfreq; /* OPB clock in Hz */
- int bi_iic_fast[2]; /* Use fast i2c mode */
-} bd_t;
-#endif /* __ASSEMBLY__ */
#ifndef NR_BOARD_IRQS
#define NR_BOARD_IRQS 0
/* TLB entry offset/size used for pinning kernel lowmem */
#define PPC44x_PIN_SHIFT 28
-#define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
+#define PPC_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
/* Lowest TLB slot consumed by the default pinned TLBs */
#define PPC44x_LOW_SLOT 63
+/*
+ * Least significant 32-bits and extended real page number (ERPN) of
+ * UART0 physical address location for early serial text debug
+ */
+#if defined(CONFIG_440SP)
+#define UART0_PHYS_ERPN 1
+#define UART0_PHYS_IO_BASE 0xf0000200
+#elif defined(CONFIG_440SPE)
+#define UART0_PHYS_ERPN 4
+#define UART0_PHYS_IO_BASE 0xf0000200
+#elif defined(CONFIG_440EP)
+#define UART0_PHYS_IO_BASE 0xe0000000
+#else
+#define UART0_PHYS_ERPN 1
+#define UART0_PHYS_IO_BASE 0x40000200
+#endif
+
+/*
+ * XXX This 36-bit trap stuff will move somewhere in syslib/
+ * when we rework/abstract the PPC44x PCI-X handling -mdp
+ */
+
/*
* Standard 4GB "page" definitions
*/
+#if defined(CONFIG_440SP)
+#define PPC44x_IO_PAGE 0x0000000100000000ULL
+#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
+#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
+#elif defined(CONFIG_440SPE)
+#define PPC44x_IO_PAGE 0x0000000400000000ULL
+#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL
+#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_PAGE 0x0000000000000000ULL
+#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
+#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
+#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
+#else
#define PPC44x_IO_PAGE 0x0000000100000000ULL
#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL
+#endif
/*
* 36-bit trap ranges
*/
-#define PPC44x_IO_LO 0x40000000
-#define PPC44x_IO_HI 0x40001000
-#define PPC44x_PCICFG_LO 0x0ec00000
-#define PPC44x_PCICFG_HI 0x0ec7ffff
-#define PPC44x_PCIMEM_LO 0x80002000
-#define PPC44x_PCIMEM_HI 0xffffffff
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define PPC44x_IO_LO 0xf0000000UL
+#define PPC44x_IO_HI 0xf0000fffUL
+#define PPC44x_PCI0CFG_LO 0x0ec00000UL
+#define PPC44x_PCI0CFG_HI 0x0ec00007UL
+#define PPC44x_PCI1CFG_LO 0x1ec00000UL
+#define PPC44x_PCI1CFG_HI 0x1ec00007UL
+#define PPC44x_PCI2CFG_LO 0x2ec00000UL
+#define PPC44x_PCI2CFG_HI 0x2ec00007UL
+#define PPC44x_PCIMEM_LO 0x80000000UL
+#define PPC44x_PCIMEM_HI 0xdfffffffUL
+#elif defined(CONFIG_440EP)
+#define PPC44x_IO_LO 0xef500000UL
+#define PPC44x_IO_HI 0xefffffffUL
+#define PPC44x_PCI0CFG_LO 0xeec00000UL
+#define PPC44x_PCI0CFG_HI 0xeecfffffUL
+#define PPC44x_PCIMEM_LO 0xa0000000UL
+#define PPC44x_PCIMEM_HI 0xdfffffffUL
+#else
+#define PPC44x_IO_LO 0x40000000UL
+#define PPC44x_IO_HI 0x40000fffUL
+#define PPC44x_PCI0CFG_LO 0x0ec00000UL
+#define PPC44x_PCI0CFG_HI 0x0ec00007UL
+#define PPC44x_PCIMEM_LO 0x80002000UL
+#define PPC44x_PCIMEM_HI 0xffffffffUL
+#endif
/*
* The "residual" board information structure the boot loader passes
*/
#ifndef __ASSEMBLY__
-/*
- * SPRN definitions
- */
-#define SPRN_CPC0_GPIO 0xe5/BEARLRL
-
/*
* DCRN definitions
*/
-#ifdef CONFIG_440GX
-/* SDRs */
+
+/* CPRs (440GX and 440SP/440SPe) */
+#define DCRN_CPR_CONFIG_ADDR 0xc
+#define DCRN_CPR_CONFIG_DATA 0xd
+
+#define DCRN_CPR_CLKUPD 0x0020
+#define DCRN_CPR_PLLC 0x0040
+#define DCRN_CPR_PLLD 0x0060
+#define DCRN_CPR_PRIMAD 0x0080
+#define DCRN_CPR_PRIMBD 0x00a0
+#define DCRN_CPR_OPBD 0x00c0
+#define DCRN_CPR_PERD 0x00e0
+#define DCRN_CPR_MALD 0x0100
+
+/* CPRs read/write helper macros */
+#define CPR_READ(offset) ({\
+ mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
+ mfdcr(DCRN_CPR_CONFIG_DATA);})
+#define CPR_WRITE(offset, data) ({\
+ mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
+ mtdcr(DCRN_CPR_CONFIG_DATA, data);})
+
+/* SDRs (440GX and 440SP/440SPe) */
#define DCRN_SDR_CONFIG_ADDR 0xe
#define DCRN_SDR_CONFIG_DATA 0xf
#define DCRN_SDR_PFC0 0x4100
#define DCRN_SDR_PFC1 0x4101
+#define DCRN_SDR_PFC1_EPS 0x1c00000
+#define DCRN_SDR_PFC1_EPS_SHIFT 22
+#define DCRN_SDR_PFC1_RMII 0x02000000
#define DCRN_SDR_MFR 0x4300
#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
#define DCRN_SDR_MFR_E3TXFH 0x00000004
#define DCRN_SDR_MFR_E3RXFL 0x00000002
#define DCRN_SDR_MFR_E3RXFH 0x00000001
+#define DCRN_SDR_UART0 0x0120
+#define DCRN_SDR_UART1 0x0121
+
+#ifdef CONFIG_440EP
+#define DCRN_SDR_UART2 0x0122
+#define DCRN_SDR_UART3 0x0123
+#define DCRN_SDR_CUST0 0x4000
+#endif
/* SDR read/write helper macros */
#define SDR_READ(offset) ({\
#define SDR_WRITE(offset, data) ({\
mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
mtdcr(DCRN_SDR_CONFIG_DATA,data);})
-#endif /* CONFIG_440GX */
-/* Base DCRNs */
+/* DMA (excluding 440SP/440SPe) */
#define DCRN_DMA0_BASE 0x100
#define DCRN_DMA1_BASE 0x108
#define DCRN_DMA2_BASE 0x110
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
#define DCRN_MAL_BASE 0x180
+#ifdef CONFIG_440EP
+#define DCRN_DMA2P40_BASE 0x300
+#define DCRN_DMA2P41_BASE 0x308
+#define DCRN_DMA2P42_BASE 0x310
+#define DCRN_DMA2P43_BASE 0x318
+#define DCRN_DMA2P4SR_BASE 0x320
+#endif
+
/* UIC */
#define DCRN_UIC0_BASE 0xc0
#define DCRN_UIC1_BASE 0xd0
#define UIC0 DCRN_UIC0_BASE
#define UIC1 DCRN_UIC1_BASE
+#ifdef CONFIG_440SPE
+#define DCRN_UIC2_BASE 0xe0
+#define DCRN_UIC3_BASE 0xf0
+#define UIC2 DCRN_UIC2_BASE
+#define UIC3 DCRN_UIC3_BASE
+#else
+#define DCRN_UIC2_BASE 0x210
+#define DCRN_UICB_BASE 0x200
+#define UIC2 DCRN_UIC2_BASE
+#define UICB DCRN_UICB_BASE
+#endif
+
#define DCRN_UIC_SR(base) (base + 0x0)
#define DCRN_UIC_ER(base) (base + 0x2)
#define DCRN_UIC_CR(base) (base + 0x3)
#define DCRN_UIC_VR(base) (base + 0x7)
#define DCRN_UIC_VCR(base) (base + 0x8)
-#define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
-#define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
+#define UIC0_UIC1NC 0x00000002
+
+#ifdef CONFIG_440SPE
+#define UIC0_UIC1NC 0x00000002
+#define UIC0_UIC2NC 0x00200000
+#define UIC0_UIC3NC 0x00008000
+#endif
+
+#define UICB_UIC0NC 0x40000000
+#define UICB_UIC1NC 0x10000000
+#define UICB_UIC2NC 0x04000000
-/* 440GP MAL DCRs */
+/* 440 MAL DCRs */
#define DCRN_MALCR(base) (base + 0x0) /* Configuration */
#define DCRN_MALESR(base) (base + 0x1) /* Error Status */
#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
-
#define MALCR_MMSR 0x80000000 /* MAL Software reset */
#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
-/* 440GP PLB Arbiter DCRs */
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+/* 440SP/440SPe PLB Arbiter DCRs */
+#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */
+#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */
+
+#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */
+#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */
+#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */
+#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */
+#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */
+
+#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */
+#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */
+#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */
+#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */
+#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */
+#else
+/* 440GP/GX PLB Arbiter DCRs */
#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */
#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
+#endif
+
+/* 440GP/GX PLB to OPB bridge DCRs */
+#define DCRN_POB0_BESR0 0x090
+#define DCRN_POB0_BESR1 0x094
+#define DCRN_POB0_BEARL 0x092
+#define DCRN_POB0_BEARH 0x093
+
+/* 440GP/GX OPB to PLB bridge DCRs */
+#define DCRN_OPB0_BSTAT 0x0a9
+#define DCRN_OPB0_BEARL 0x0aa
+#define DCRN_OPB0_BEARH 0x0ab
/* 440GP Clock, PM, chip control */
#define DCRN_CPC0_SR 0x0b0
#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
-/* 440GP DRAM controller DCRs */
+/* 440GP/440GX SDRAM controller DCRs */
#define DCRN_SDRAM0_CFGADDR 0x010
#define DCRN_SDRAM0_CFGDATA 0x011
#define PPC44x_MEM_SIZE_128M 0x08000000
#define PPC44x_MEM_SIZE_256M 0x10000000
#define PPC44x_MEM_SIZE_512M 0x20000000
+#define PPC44x_MEM_SIZE_1G 0x40000000
+#define PPC44x_MEM_SIZE_2G 0x80000000
+
+/* 440SP/440SPe memory controller DCRs */
+#define DCRN_MQ0_BS0BAS 0x40
+#if defined(CONFIG_440SP)
+#define MQ0_NUM_BANKS 2
+#elif defined(CONFIG_440SPE)
+#define MQ0_NUM_BANKS 4
+#endif
+
+#define MQ0_CONFIG_SIZE_MASK 0x0000fff0
+#define MQ0_CONFIG_SIZE_8M 0x0000ffc0
+#define MQ0_CONFIG_SIZE_16M 0x0000ff80
+#define MQ0_CONFIG_SIZE_32M 0x0000ff00
+#define MQ0_CONFIG_SIZE_64M 0x0000fe00
+#define MQ0_CONFIG_SIZE_128M 0x0000fc00
+#define MQ0_CONFIG_SIZE_256M 0x0000f800
+#define MQ0_CONFIG_SIZE_512M 0x0000f000
+#define MQ0_CONFIG_SIZE_1G 0x0000e000
+#define MQ0_CONFIG_SIZE_2G 0x0000c000
+#define MQ0_CONFIG_SIZE_4G 0x00008000
+
+/* Internal SRAM Controller 440GX/440SP/440SPe */
+#define DCRN_SRAM0_BASE 0x000
+
+#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
+#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)
+#define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022)
+#define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023)
+#define SRAM_SBCR_BAS0 0x80000000
+#define SRAM_SBCR_BAS1 0x80010000
+#define SRAM_SBCR_BAS2 0x80020000
+#define SRAM_SBCR_BAS3 0x80030000
+#define SRAM_SBCR_BU_MASK 0x00000180
+#define SRAM_SBCR_BS_64KB 0x00000800
+#define SRAM_SBCR_BU_RO 0x00000080
+#define SRAM_SBCR_BU_RW 0x00000180
+#define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024)
+#define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025)
+#define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026)
+#define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027)
+#define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028)
+#define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029)
+#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a)
+#define SRAM_DPC_ENABLE 0x80000000
+
+/* L2 Cache Controller 440GX/440SP/440SPe */
+#define DCRN_L2C0_CFG 0x030
+#define L2C_CFG_L2M 0x80000000
+#define L2C_CFG_ICU 0x40000000
+#define L2C_CFG_DCU 0x20000000
+#define L2C_CFG_DCW_MASK 0x1e000000
+#define L2C_CFG_TPC 0x01000000
+#define L2C_CFG_CPC 0x00800000
+#define L2C_CFG_FRAN 0x00200000
+#define L2C_CFG_SS_MASK 0x00180000
+#define L2C_CFG_SS_256 0x00000000
+#define L2C_CFG_CPIM 0x00040000
+#define L2C_CFG_TPIM 0x00020000
+#define L2C_CFG_LIM 0x00010000
+#define L2C_CFG_PMUX_MASK 0x00007000
+#define L2C_CFG_PMUX_SNP 0x00000000
+#define L2C_CFG_PMUX_IF 0x00001000
+#define L2C_CFG_PMUX_DF 0x00002000
+#define L2C_CFG_PMUX_DS 0x00003000
+#define L2C_CFG_PMIM 0x00000800
+#define L2C_CFG_TPEI 0x00000400
+#define L2C_CFG_CPEI 0x00000200
+#define L2C_CFG_NAM 0x00000100
+#define L2C_CFG_SMCM 0x00000080
+#define L2C_CFG_NBRM 0x00000040
+#define DCRN_L2C0_CMD 0x031
+#define L2C_CMD_CLR 0x80000000
+#define L2C_CMD_DIAG 0x40000000
+#define L2C_CMD_INV 0x20000000
+#define L2C_CMD_CCP 0x10000000
+#define L2C_CMD_CTE 0x08000000
+#define L2C_CMD_STRC 0x04000000
+#define L2C_CMD_STPC 0x02000000
+#define L2C_CMD_RPMC 0x01000000
+#define L2C_CMD_HCC 0x00800000
+#define DCRN_L2C0_ADDR 0x032
+#define DCRN_L2C0_DATA 0x033
+#define DCRN_L2C0_SR 0x034
+#define L2C_SR_CC 0x80000000
+#define L2C_SR_CPE 0x40000000
+#define L2C_SR_TPE 0x20000000
+#define L2C_SR_LRU 0x10000000
+#define L2C_SR_PCS 0x08000000
+#define DCRN_L2C0_REVID 0x035
+#define DCRN_L2C0_SNP0 0x036
+#define DCRN_L2C0_SNP1 0x037
+#define L2C_SNP_BA_MASK 0xffff0000
+#define L2C_SNP_SSR_MASK 0x0000f000
+#define L2C_SNP_SSR_32G 0x0000f000
+#define L2C_SNP_ESR 0x00000800
/*
* PCI-X definitions
*/
-#define PCIX0_REG_BASE 0x20ec80000ULL
-#define PCIX0_REG_SIZE 0x200
+#define PCIX0_CFGA 0x0ec00000UL
+#define PCIX1_CFGA 0x1ec00000UL
+#define PCIX2_CFGA 0x2ec00000UL
+#define PCIX0_CFGD 0x0ec00004UL
+#define PCIX1_CFGD 0x1ec00004UL
+#define PCIX2_CFGD 0x2ec00004UL
+
+#define PCIX0_IO_BASE 0x0000000908000000ULL
+#define PCIX1_IO_BASE 0x0000000908000000ULL
+#define PCIX2_IO_BASE 0x0000000908000000ULL
+#define PCIX_IO_SIZE 0x00010000
+
+#ifdef CONFIG_440SP
+#define PCIX0_REG_BASE 0x000000090ec80000ULL
+#else
+#define PCIX0_REG_BASE 0x000000020ec80000ULL
+#endif
+#define PCIX_REG_OFFSET 0x10000000
+#define PCIX_REG_SIZE 0x200
#define PCIX0_VENDID 0x000
#define PCIX0_DEVID 0x002
#define IIC_CLOCK 50
#undef NR_UICS
+#if defined(CONFIG_440GX)
+#define NR_UICS 3
+#elif defined(CONFIG_440SPE)
+#define NR_UICS 4
+#else
#define NR_UICS 2
-#define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
+#endif
#include <asm/ibm4xx.h>
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