vserver 1.9.3

[linux-2.6.git] / include / asm-ppc / io.h

diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 8bfae09..5abdd42 100644 (file)
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -4,7 +4,6 @@
 
 #include <linux/config.h>
 #include <linux/types.h>
-#include <linux/mm.h>
 
 #include <asm/page.h>
 #include <asm/byteorder.h>
@@ -30,6 +29,8 @@
 #include <asm/mpc8xx.h>
 #elif defined(CONFIG_8260)
 #include <asm/mpc8260.h>
+#elif defined(CONFIG_85xx)
+#include <asm/mpc85xx.h>
 #elif defined(CONFIG_APUS)
 #define _IO_BASE       0
 #define _ISA_MEM_BASE  0
@@ -138,18 +139,27 @@ extern __inline__ void name(unsigned int val, unsigned int port) \
                : : "r" (val), "r" (port + _IO_BASE));  \
 }
 
-__do_in_asm(inb, "lbzx")
 __do_out_asm(outb, "stbx")
 #ifdef CONFIG_APUS
+__do_in_asm(inb, "lbzx")
 __do_in_asm(inw, "lhz%U1%X1")
 __do_in_asm(inl, "lwz%U1%X1")
 __do_out_asm(outl,"stw%U0%X0")
 __do_out_asm(outw, "sth%U0%X0")
+#elif defined (CONFIG_8260_PCI9)
+/* in asm cannot be defined if PCI9 workaround is used */
+#define inb(port)              in_8((u8 *)((port)+_IO_BASE))
+#define inw(port)              in_le16((u16 *)((port)+_IO_BASE))
+#define inl(port)              in_le32((u32 *)((port)+_IO_BASE))
+__do_out_asm(outw, "sthbrx")
+__do_out_asm(outl, "stwbrx")
 #else
+__do_in_asm(inb, "lbzx")
 __do_in_asm(inw, "lhbrx")
 __do_in_asm(inl, "lwbrx")
 __do_out_asm(outw, "sthbrx")
 __do_out_asm(outl, "stwbrx")
+
 #endif
 
 #define inb_p(port)            inb((port))
@@ -226,7 +236,7 @@ extern inline void * bus_to_virt(unsigned long address)
 {
 #ifndef CONFIG_APUS
         if (address == 0)
-               return 0;
+               return NULL;
         return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
 #else
        return (void*) mm_ptov (address);
@@ -388,43 +398,83 @@ static inline int isa_check_signature(unsigned long io_addr,
        return 0;
 }
 
-#ifdef CONFIG_NOT_COHERENT_CACHE
-
 /*
- * DMA-consistent mapping functions for PowerPCs that don't support
- * cache snooping.  These allocate/free a region of uncached mapped
- * memory space for use with DMA devices.  Alternatively, you could
- * allocate the space "normally" and use the cache management functions
- * to ensure it is consistent.
+ * Here comes the ppc implementation of the IOMAP 
+ * interfaces.
  */
-extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
-extern void consistent_free(void *vaddr);
-extern void consistent_sync(void *vaddr, size_t size, int rw);
-extern void consistent_sync_page(struct page *page, unsigned long offset,
-                                size_t size, int rw);
+static inline unsigned int ioread8(void __iomem *addr)
+{
+       return readb(addr);
+}
 
-#define dma_cache_inv(_start,_size) \
-       invalidate_dcache_range(_start, (_start + _size))
-#define dma_cache_wback(_start,_size) \
-       clean_dcache_range(_start, (_start + _size))
-#define dma_cache_wback_inv(_start,_size) \
-       flush_dcache_range(_start, (_start + _size))
+static inline unsigned int ioread16(void __iomem *addr)
+{
+       return readw(addr);
+}
 
-#else /* ! CONFIG_NOT_COHERENT_CACHE */
+static inline unsigned int ioread32(void __iomem *addr)
+{
+       return readl(addr);
+}
 
-/*
- * Cache coherent cores.
- */
+static inline void iowrite8(u8 val, void __iomem *addr)
+{
+       writeb(val, addr);
+}
 
-#define dma_cache_inv(_start,_size)            do { } while (0)
-#define dma_cache_wback(_start,_size)          do { } while (0)
-#define dma_cache_wback_inv(_start,_size)      do { } while (0)
+static inline void iowrite16(u16 val, void __iomem *addr)
+{
+       writew(val, addr);
+}
 
-#define consistent_alloc(gfp, size, handle)    NULL
-#define consistent_free(addr)                  do { } while (0)
-#define consistent_sync(addr, size, rw)                do { } while (0)
-#define consistent_sync_page(pg, off, sz, rw)  do { } while (0)
+static inline void iowrite32(u32 val, void __iomem *addr)
+{
+       writel(val, addr);
+}
+
+static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+       _insb((u8 __force *) addr, dst, count);
+}
+
+static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+       _insw_ns((u16 __force *) addr, dst, count);
+}
+
+static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+       _insl_ns((u32 __force *) addr, dst, count);
+}
+
+static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+       _outsb((u8 __force *) addr, src, count);
+}
+
+static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+       _outsw_ns((u16 __force *) addr, src, count);
+}
+
+static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+       _outsl_ns((u32 __force *) addr, src, count);
+}
+
+/* Create a virtual mapping cookie for an IO port range */
+extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
+extern void ioport_unmap(void __iomem *);
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 
-#endif /* ! CONFIG_NOT_COHERENT_CACHE */
 #endif /* _PPC_IO_H */
+
+#ifdef CONFIG_8260_PCI9
+#include <asm/mpc8260_pci9.h>
+#endif
+
 #endif /* __KERNEL__ */