vserver 1.9.3

[linux-2.6.git] / include / asm-ppc64 / processor.h

diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index d3e8310..19ef025 100644 (file)
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -20,12 +20,6 @@
 #include <asm/ptrace.h>
 #include <asm/types.h>
 
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
 /* Machine State Register (MSR) Fields */
 #define MSR_SF_LG      63              /* Enable 64 bit mode */
 #define MSR_ISF_LG     61              /* Interrupt 64b mode valid on 630 */
@@ -348,7 +342,7 @@
 #define        PVR     SPRN_PVR        /* Processor Version */
 #define        PIR     SPRN_PIR        /* Processor ID */
 #define        PURR    SPRN_PURR       /* Processor Utilization of Resource Register */
-#define        RPA     SPRN_RPA        /* Required Physical Address Register */
+//#define      RPA     SPRN_RPA        /* Required Physical Address Register */
 #define        SDR1    SPRN_SDR1       /* MMU hash base register */
 #define        SPR0    SPRN_SPRG0      /* Supervisor Private Registers */
 #define        SPR1    SPRN_SPRG1
@@ -382,8 +376,10 @@
 #define        PV_ICESTAR      0x0036
 #define        PV_SSTAR        0x0037
 #define        PV_POWER4p      0x0038
-#define PV_GPUL                0x0039
+#define PV_970         0x0039
 #define        PV_POWER5       0x003A
+#define PV_POWER5p     0x003B
+#define PV_970FX       0x003C
 #define        PV_630          0x0040
 #define        PV_630p         0x0041
 
@@ -408,6 +404,12 @@
 #define XGLUE(a,b) a##b
 #define GLUE(a,b) XGLUE(a,b)
 
+/* iSeries CTRL register (for runlatch) */
+
+#define CTRLT          0x098
+#define CTRLF          0x088
+#define RUNLATCH       0x0001
+
 #ifdef __ASSEMBLY__
 
 #define _GLOBAL(name) \
@@ -436,8 +438,13 @@ name: \
        .type GLUE(.,name),@function; \
 GLUE(.,name):
 
-#endif /* __ASSEMBLY__ */
+#else /* __ASSEMBLY__ */
 
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
 
 /* Macros for setting and retrieving special purpose registers */
 
@@ -459,20 +466,9 @@ GLUE(.,name):
 #define mttbl(v)       asm volatile("mttbl %0":: "r"(v))
 #define mttbu(v)       asm volatile("mttbu %0":: "r"(v))
 
-/* iSeries CTRL register (for runlatch) */
-
-#define CTRLT          0x098
-#define CTRLF          0x088
-#define RUNLATCH       0x0001
-
-/* Size of an exception stack frame contained in the paca. */
-#define EXC_FRAME_SIZE 64
-
 #define mfasr()                ({unsigned long rval; \
                        asm volatile("mfasr %0" : "=r" (rval)); rval;})
 
-#ifndef __ASSEMBLY__
-
 static inline void set_tb(unsigned int upper, unsigned int lower)
 {
        mttbl(0);
@@ -483,6 +479,8 @@ static inline void set_tb(unsigned int upper, unsigned int lower)
 #define __get_SP()     ({unsigned long sp; \
                        asm volatile("mr %0,1": "=r" (sp)); sp;})
 
+#ifdef __KERNEL__
+
 extern int have_of;
 
 struct task_struct;
@@ -505,8 +503,6 @@ extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 extern struct task_struct *last_task_used_math;
 extern struct task_struct *last_task_used_altivec;
 
-
-#ifdef __KERNEL__
 /* 64-bit user address space is 41-bits (2TBs user VM) */
 #define TASK_SIZE_USER64 (0x0000020000000000UL)
 
@@ -518,8 +514,6 @@ extern struct task_struct *last_task_used_altivec;
 
 #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
                TASK_SIZE_USER32 : TASK_SIZE_USER64)
-#endif /* __KERNEL__ */
-
 
 /* This decides where the kernel will search for a free chunk of vm
  * space during mmap's.
@@ -536,13 +530,13 @@ typedef struct {
 
 struct thread_struct {
        unsigned long   ksp;            /* Kernel stack pointer */
+       unsigned long   ksp_vsid;
        struct pt_regs  *regs;          /* Pointer to saved register state */
        mm_segment_t    fs;             /* for get_fs() validation */
        double          fpr[32];        /* Complete floating point set */
        unsigned long   fpscr;          /* Floating point status (plus pad) */
        unsigned long   fpexc_mode;     /* Floating-point exception mode */
-       unsigned long   saved_msr;      /* Save MSR across signal handlers */
-       unsigned long   saved_softe;    /* Ditto for Soft Enable/Disable */
+       unsigned long   pad[3];         /* was saved_msr, saved_softe */
 #ifdef CONFIG_ALTIVEC
        /* Complete AltiVec register set */
        vector128       vr[32] __attribute((aligned(16)));
@@ -558,12 +552,12 @@ struct thread_struct {
 #define INIT_SP                (sizeof(init_stack) + (unsigned long) &init_stack)
 
 #define INIT_THREAD  { \
-       INIT_SP, /* ksp */ \
-       (struct pt_regs *)INIT_SP - 1, /* regs */ \
-       KERNEL_DS, /*fs*/ \
-       {0}, /* fpr */ \
-       0, /* fpscr */ \
-       MSR_FE0|MSR_FE1, /* fpexc_mode */ \
+       .ksp = INIT_SP, \
+       .regs = (struct pt_regs *)INIT_SP - 1, \
+       .fs = KERNEL_DS, \
+       .fpr = {0}, \
+       .fpscr = 0, \
+       .fpexc_mode = MSR_FE0|MSR_FE1, \
 }
 
 /*
@@ -625,6 +619,16 @@ static inline void prefetchw(const void *x)
 
 #define spin_lock_prefetch(x)  prefetchw(x)
 
-#endif /* ASSEMBLY */
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Number of entries in the SLB. If this ever changes we should handle
+ * it with a use a cpu feature fixup.
+ */
+#define SLB_NUM_ENTRIES 64
 
 #endif /* __ASM_PPC64_PROCESSOR_H */