#include <asm/types.h>
#include <asm/ptrace.h>
#include <asm/setup.h>
+#include <asm/processor.h>
#ifdef __KERNEL__
prev = __switch_to(prev,next); \
} while (0)
-#define prepare_arch_switch(rq, next) do { } while(0)
-#define task_running(rq, p) ((rq)->curr == (p))
-#define finish_arch_switch(rq, prev) do { \
+/*
+ * On SMP systems, when the scheduler does migration-cost autodetection,
+ * it needs a way to flush as much of the CPU's caches as possible.
+ *
+ * TODO: fill this in!
+ */
+static inline void sched_cacheflush(void)
+{
+}
+
+#ifdef CONFIG_VIRT_CPU_ACCOUNTING
+extern void account_vtime(struct task_struct *);
+extern void account_tick_vtime(struct task_struct *);
+extern void account_system_vtime(struct task_struct *);
+#else
+#define account_vtime(x) do { /* empty */ } while (0)
+#endif
+
+#define finish_arch_switch(prev) do { \
set_fs(current->thread.mm_segment); \
- spin_unlock_irq(&(rq)->lock); \
+ account_vtime(prev); \
} while (0)
#define nop() __asm__ __volatile__ ("nop")
#ifdef __s390x__
-#define __load_psw(psw) \
- __asm__ __volatile__("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc" );
-
#define __ctl_load(array, low, high) ({ \
+ typedef struct { char _[sizeof(array)]; } addrtype; \
__asm__ __volatile__ ( \
" bras 1,0f\n" \
" lctlg 0,0,0(%0)\n" \
"0: ex %1,0(1)" \
- : : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
+ : : "a" (&array), "a" (((low)<<4)+(high)), \
+ "m" (*(addrtype *)(array)) : "1" ); \
})
#define __ctl_store(array, low, high) ({ \
+ typedef struct { char _[sizeof(array)]; } addrtype; \
__asm__ __volatile__ ( \
" bras 1,0f\n" \
" stctg 0,0,0(%1)\n" \
"0: ex %2,0(1)" \
- : "=m" (array) : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
+ : "=m" (*(addrtype *)(array)) \
+ : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
})
#define __ctl_set_bit(cr, bit) ({ \
#else /* __s390x__ */
-#define __load_psw(psw) \
- __asm__ __volatile__("lpsw 0(%0)" : : "a" (&psw) : "cc" );
-
#define __ctl_load(array, low, high) ({ \
+ typedef struct { char _[sizeof(array)]; } addrtype; \
__asm__ __volatile__ ( \
" bras 1,0f\n" \
" lctl 0,0,0(%0)\n" \
"0: ex %1,0(1)" \
- : : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
+ : : "a" (&array), "a" (((low)<<4)+(high)), \
+ "m" (*(addrtype *)(array)) : "1" ); \
})
#define __ctl_store(array, low, high) ({ \
+ typedef struct { char _[sizeof(array)]; } addrtype; \
__asm__ __volatile__ ( \
" bras 1,0f\n" \
" stctl 0,0,0(%1)\n" \
"0: ex %2,0(1)" \
- : "=m" (array) : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
+ : "=m" (*(addrtype *)(array)) \
+ : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
})
#define __ctl_set_bit(cr, bit) ({ \
/* For spinlocks etc */
#define local_irq_save(x) ((x) = local_irq_disable())
+/*
+ * Use to set psw mask except for the first byte which
+ * won't be changed by this function.
+ */
+static inline void
+__set_psw_mask(unsigned long mask)
+{
+ local_save_flags(mask);
+ __load_psw_mask(mask);
+}
+
+#define local_mcck_enable() __set_psw_mask(PSW_KERNEL_BITS)
+#define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)
+
#ifdef CONFIG_SMP
extern void smp_ctl_set_bit(int cr, int bit);
extern void (*_machine_halt)(void);
extern void (*_machine_power_off)(void);
+#define arch_align_stack(x) (x)
+
#endif /* __KERNEL__ */
#endif