#define iowrite32_rep(a,s,c) outsl(a,s,c)
/* Memory functions, same as I/O accesses on Ultra. */
-static inline u8 _readb(void __iomem *addr)
+static inline u8 _readb(const volatile void __iomem *addr)
{ u8 ret;
__asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */"
return ret;
}
-static inline u16 _readw(void __iomem *addr)
+static inline u16 _readw(const volatile void __iomem *addr)
{ u16 ret;
__asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */"
return ret;
}
-static inline u32 _readl(void __iomem *addr)
+static inline u32 _readl(const volatile void __iomem *addr)
{ u32 ret;
__asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */"
return ret;
}
-static inline u64 _readq(void __iomem *addr)
+static inline u64 _readq(const volatile void __iomem *addr)
{ u64 ret;
__asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */"
return ret;
}
-static inline void _writeb(u8 b, void __iomem *addr)
+static inline void _writeb(u8 b, volatile void __iomem *addr)
{
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */"
: /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}
-static inline void _writew(u16 w, void __iomem *addr)
+static inline void _writew(u16 w, volatile void __iomem *addr)
{
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */"
: /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}
-static inline void _writel(u32 l, void __iomem *addr)
+static inline void _writel(u32 l, volatile void __iomem *addr)
{
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */"
: /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L));
}
-static inline void _writeq(u64 q, void __iomem *addr)
+static inline void _writeq(u64 q, volatile void __iomem *addr)
{
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
: /* no outputs */
/* Now, SBUS variants, only difference from PCI is that we do
* not use little-endian ASIs.
*/
-static inline u8 _sbus_readb(void __iomem *addr)
+static inline u8 _sbus_readb(const volatile void __iomem *addr)
{
u8 ret;
return ret;
}
-static inline u16 _sbus_readw(void __iomem *addr)
+static inline u16 _sbus_readw(const volatile void __iomem *addr)
{
u16 ret;
return ret;
}
-static inline u32 _sbus_readl(void __iomem *addr)
+static inline u32 _sbus_readl(const volatile void __iomem *addr)
{
u32 ret;
return ret;
}
-static inline u64 _sbus_readq(void __iomem *addr)
+static inline u64 _sbus_readq(const volatile void __iomem *addr)
{
u64 ret;
return ret;
}
-static inline void _sbus_writeb(u8 b, void __iomem *addr)
+static inline void _sbus_writeb(u8 b, volatile void __iomem *addr)
{
__asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */"
: /* no outputs */
: "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}
-static inline void _sbus_writew(u16 w, void __iomem *addr)
+static inline void _sbus_writew(u16 w, volatile void __iomem *addr)
{
__asm__ __volatile__("stha\t%r0, [%1] %2\t/* sbus_writew */"
: /* no outputs */
: "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}
-static inline void _sbus_writel(u32 l, void __iomem *addr)
+static inline void _sbus_writel(u32 l, volatile void __iomem *addr)
{
__asm__ __volatile__("stwa\t%r0, [%1] %2\t/* sbus_writel */"
: /* no outputs */
: "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
}
-static inline void _sbus_writeq(u64 l, void __iomem *addr)
+static inline void _sbus_writeq(u64 l, volatile void __iomem *addr)
{
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */"
: /* no outputs */
#define sbus_writel(__l, __addr) _sbus_writel(__l, __addr)
#define sbus_writeq(__l, __addr) _sbus_writeq(__l, __addr)
-static inline void __iomem*_sbus_memset_io(void __iomem *dst, int c,
- __kernel_size_t n)
+static inline void _sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
{
while(n--) {
sbus_writeb(c, dst);
dst++;
}
- return (void *) dst;
}
#define sbus_memset_io(d,c,sz) _sbus_memset_io(d,c,sz)
-static inline void __iomem *
-_memset_io(void __iomem *dst, int c, __kernel_size_t n)
+static inline void
+_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n)
{
- void __iomem *d = dst;
+ volatile void __iomem *d = dst;
while (n--) {
writeb(c, d);
d++;
}
-
- return dst;
}
#define memset_io(d,c,sz) _memset_io(d,c,sz)
-static inline void __iomem *
-_memcpy_fromio(void *dst, void __iomem *src, __kernel_size_t n)
+static inline void
+_memcpy_fromio(void *dst, const volatile void __iomem *src, __kernel_size_t n)
{
char *d = dst;
*d++ = tmp;
src++;
}
-
- return dst;
}
#define memcpy_fromio(d,s,sz) _memcpy_fromio(d,s,sz)
-static inline void __iomem *
-_memcpy_toio(void __iomem *dst, const void *src, __kernel_size_t n)
+static inline void
+_memcpy_toio(volatile void __iomem *dst, const void *src, __kernel_size_t n)
{
const char *s = src;
- void __iomem *d = dst;
+ volatile void __iomem *d = dst;
while (n--) {
char tmp = *s++;
writeb(tmp, d);
d++;
}
- return dst;
}
#define memcpy_toio(d,s,sz) _memcpy_toio(d,s,sz)
-static inline int check_signature(unsigned long io_addr,
+static inline int check_signature(void __iomem *io_addr,
const unsigned char *signature,
int length)
{
int retval = 0;
do {
- if (readb((void __iomem *)io_addr) != *signature++)
+ if (readb(io_addr) != *signature++)
goto out;
io_addr++;
} while (--length);
return retval;
}
+#define mmiowb()
+
#ifdef __KERNEL__
/* On sparc64 we have the whole physical IO address space accessible
* using physically addressed loads and stores, so this does nothing.
*/
-#define ioremap(__offset, __size) ((void __iomem *)(__offset))
+static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
+{
+ return (void __iomem *)offset;
+}
+
#define ioremap_nocache(X,Y) ioremap((X),(Y))
-#define iounmap(__addr) do { (void)(__addr); } while(0)
+
+static inline void iounmap(volatile void __iomem *addr)
+{
+}
#define ioread8(X) readb(X)
#define ioread16(X) readw(X)