#include <asm/io.h>
#include <asm/page.h>
#include <asm/oplib.h>
+#include <asm/prom.h>
+#include <asm/of_device.h>
#include <asm/iommu.h>
/* The abstraction used here is that there are PCI controllers,
* PCI bus.
*/
-#define PBM_LOGCLUSTERS 3
-#define PBM_NCLUSTERS (1 << PBM_LOGCLUSTERS)
-
struct pci_controller_info;
/* This contains the software state necessary to drive a PCI
* controller's IOMMU.
*/
+struct pci_iommu_arena {
+ unsigned long *map;
+ unsigned int hint;
+ unsigned int limit;
+};
+
struct pci_iommu {
/* This protects the controller's IOMMU and all
* streaming buffers underneath.
*/
spinlock_t lock;
+ struct pci_iommu_arena arena;
+
/* IOMMU page table, a linear array of ioptes. */
iopte_t *page_table; /* The page table itself. */
- int page_table_sz_bits; /* log2 of ow many pages does it map? */
/* Base PCI memory space address where IOMMU mappings
* begin.
*/
unsigned long write_complete_reg;
- /* The lowest used consistent mapping entry. Since
- * we allocate consistent maps out of cluster 0 this
- * is relative to the beginning of closter 0.
- */
- u32 lowest_consistent_map;
-
/* In order to deal with some buggy third-party PCI bridges that
* do wrong prefetching, we never mark valid mappings as invalid.
* Instead we point them at this dummy page.
unsigned long dummy_page;
unsigned long dummy_page_pa;
- /* If PBM_NCLUSTERS is ever decreased to 4 or lower,
- * or if largest supported page_table_sz * 8K goes above
- * 2GB, you must increase the size of the type of
- * these counters. You have been duly warned. -DaveM
- */
- struct {
- u16 next;
- u16 flush;
- } alloc_info[PBM_NCLUSTERS];
-
/* CTX allocation. */
unsigned long ctx_lowest_free;
unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
u32 dma_addr_mask;
};
-extern void pci_iommu_table_init(struct pci_iommu *, int);
+extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
/* This describes a PCI bus module's streaming buffer. */
struct pci_strbuf {
/* Physical address base of PBM registers. */
unsigned long pbm_regs;
+ /* Physical address of DMA sync register, if any. */
+ unsigned long sync_reg;
+
/* Opaque 32-bit system bus Port ID. */
u32 portid;
+ /* Opaque 32-bit handle used for hypervisor calls. */
+ u32 devhandle;
+
/* Chipset version information. */
int chip_type;
#define PBM_CHIP_TYPE_SABRE 1
int chip_revision;
/* Name used for top-level resources. */
- char name[64];
+ char *name;
/* OBP specific information. */
- int prom_node;
- char prom_name[64];
- struct linux_prom_pci_ranges pbm_ranges[PROM_PCIRNG_MAX];
+ struct device_node *prom_node;
+ struct linux_prom_pci_ranges *pbm_ranges;
int num_pbm_ranges;
- struct linux_prom_pci_intmap pbm_intmap[PROM_PCIIMAP_MAX];
+ struct linux_prom_pci_intmap *pbm_intmap;
int num_pbm_intmap;
- struct linux_prom_pci_intmask pbm_intmask;
+ struct linux_prom_pci_intmask *pbm_intmask;
u64 ino_bitmap;
/* PBM I/O and Memory space resources. */
/* Operations which are controller specific. */
void (*scan_bus)(struct pci_controller_info *);
- unsigned int (*irq_build)(struct pci_pbm_info *, struct pci_dev *, unsigned int);
void (*base_address_update)(struct pci_dev *, int);
void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
struct pci_ops *pci_ops;
unsigned int pci_first_busno;
unsigned int pci_last_busno;
-
- void *starfire_cookie;
};
/* PCI devices which are not bridges have this placed in their pci_dev
*/
struct pcidev_cookie {
struct pci_pbm_info *pbm;
- char prom_name[64];
- int prom_node;
+ struct device_node *prom_node;
+ struct of_device *op;
struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
int num_prom_regs;
struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];